A Novel Circuit Technology with Surrounding Gate Transistors (SGT's) for Ultra High Density DRAM's

Kazunori Ohuchi, Shigeyoshi Watanabe, Kenji Tsuchida, Daisaburo Takashima, Yukihito Oowaki, Kazumasa Sunouchi, Akihiro Nitayama, Katsuhiko Hieda, Hirishi Takato, Akihiro Nitayama, Katsuhiko Hieda, Hirishi Takato, Fumio Horiguchi, Fujio Masuoka, Hisashi Hara

研究成果: Article査読

46 被引用数 (Scopus)

抄録

This paper describes a novel circuit technology with Surrounding Gate Transistors (SGT's) for ultra high density DRAM's. In order to reduce the chip size drastically, an SGT is employed to all the transistors within a chip. SGT's connected in series and a common source SGT have been newly developed for the core circuit, such as a sense amplifier designed by a tight design rule. Furthermore, to reduce the inherent cell array noise caused by a relaxed open bit line (BL) architecture, a noise killer circuit placed in the word line (WL) shunt region and a twisted BL architecture within the sense amplifier region combined with a novel separation sensing scheme have been newly introduced. Using the novel circuit technology, a 32.9% smaller chip size can be successfully achieved for a 64-Mb DRAM and 34.4% for a 1-Gb DRAM compared with a DRAM composed of the planar transistor without sacrificing the access time, power dissipation, and Vcc margin. Furthermore, the effectiveness of this technology is verified by using the circuit simulation of the internal main nodes such as WL and BL.

本文言語English
ページ(範囲)960-971
ページ数12
ジャーナルIEEE Journal of Solid-State Circuits
30
9
DOI
出版ステータスPublished - 1995 9月

ASJC Scopus subject areas

  • 電子工学および電気工学

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