A new vertically stacked poly-Si MOSFET for 533MHz high speed 64Mbit SRAM

T. Kikuchi, S. Moriya, Y. Nakatsuka, H. Matsuoka, K. Nakazato, A. Nishida, H. Chakihara, M. Matsuoka, M. Moniwa

    研究成果: Conference article査読

    10 被引用数 (Scopus)

    抄録

    A New Vertically Stacked Poly-Si MOSFET has been studied as a novel technique that enables device integration without applying advanced node process. Reduced cell area size of 1.21μm2 has been achieved in 6T-SRAM which is 60% of 130nm node based planer type cell. Operation speed of 533MHz was also confirmed.

    本文言語English
    ページ(範囲)923-926
    ページ数4
    ジャーナルTechnical Digest - International Electron Devices Meeting, IEDM
    出版ステータスPublished - 2004
    イベントIEEE International Electron Devices Meeting, 2004 IEDM - San Francisco, CA, United States
    継続期間: 2004 12 132004 12 15

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Condensed Matter Physics
    • Electrical and Electronic Engineering
    • Materials Chemistry

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