A new vertically stacked poly-Si MOSFET for 533MHz high speed 64Mbit SRAM

T. Kikuchi; S. Moriya; Y. Nakatsuka; H. Matsuoka; K. Nakazato; A. Nishida; H. Chakihara; M. Matsuoka; M. Moniwa

A new vertically stacked poly-Si MOSFET for 533MHz high speed 64Mbit SRAM

T. Kikuchi, S. Moriya, Y. Nakatsuka, H. Matsuoka, K. Nakazato, A. Nishida, H. Chakihara, M. Matsuoka, M. Moniwa

研究成果: Conference article › 査読

抄録

A New Vertically Stacked Poly-Si MOSFET has been studied as a novel technique that enables device integration without applying advanced node process. Reduced cell area size of 1.21μm² has been achieved in 6T-SRAM which is 60% of 130nm node based planer type cell. Operation speed of 533MHz was also confirmed.

本文言語	English
ページ（範囲）	923-926
ページ数	4
ジャーナル	Technical Digest - International Electron Devices Meeting, IEDM
出版ステータス	Published - 2004
イベント	IEEE International Electron Devices Meeting, 2004 IEDM - San Francisco, CA, United States 継続期間: 2004 12 13 → 2004 12 15

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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引用スタイル

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abstract = "A New Vertically Stacked Poly-Si MOSFET has been studied as a novel technique that enables device integration without applying advanced node process. Reduced cell area size of 1.21μm2 has been achieved in 6T-SRAM which is 60% of 130nm node based planer type cell. Operation speed of 533MHz was also confirmed.",

author = "T. Kikuchi and S. Moriya and Y. Nakatsuka and H. Matsuoka and K. Nakazato and A. Nishida and H. Chakihara and M. Matsuoka and M. Moniwa",

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T1 - A new vertically stacked poly-Si MOSFET for 533MHz high speed 64Mbit SRAM

AU - Kikuchi, T.

AU - Moriya, S.

AU - Nakatsuka, Y.

AU - Matsuoka, H.

AU - Nakazato, K.

AU - Nishida, A.

AU - Chakihara, H.

AU - Matsuoka, M.

AU - Moniwa, M.

PY - 2004

Y1 - 2004

N2 - A New Vertically Stacked Poly-Si MOSFET has been studied as a novel technique that enables device integration without applying advanced node process. Reduced cell area size of 1.21μm2 has been achieved in 6T-SRAM which is 60% of 130nm node based planer type cell. Operation speed of 533MHz was also confirmed.

AB - A New Vertically Stacked Poly-Si MOSFET has been studied as a novel technique that enables device integration without applying advanced node process. Reduced cell area size of 1.21μm2 has been achieved in 6T-SRAM which is 60% of 130nm node based planer type cell. Operation speed of 533MHz was also confirmed.

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M3 - Conference article

AN - SCOPUS:21644470779

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JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

SN - 0163-1918

T2 - IEEE International Electron Devices Meeting, 2004 IEDM

Y2 - 13 December 2004 through 15 December 2004

ER -