A new digital architecture of inverse function delayed neuron with the stochastic logic

Hongge Li, Yoshihiro Hayakawa, Shigeo Sato, Koji Nakajima

研究成果: Conference article査読

1 被引用数 (Scopus)

抄録

In this paper, we present a new digital architecture of the neuron hardware that can be implemented using a field programmable gate array (FPGA). The proposed neuron applies a new Inverse Function Delayed Neuron model. In order to decrease the circuit area, we employ the stochastic logic. Because of the property of pseudo-analog operations of stochastic logic, the scale of a circuit is smaller than a conventional digital circuit. However, the stochastic logic requires the certain accumulation time for the more precise mean. Fortunately, the ID model of high-speed convergence remedies this shortcoming. The simulation experimental results show that the inverse function variance is related to the accumulation time, and this digital system can perform the associative memory.

本文言語English
ジャーナルMidwest Symposium on Circuits and Systems
2
出版ステータスPublished - 2004 12 1
イベントThe 2004 47th Midwest Symposium on Circuits and Systems - Conference Proceedings - Hiroshima, Japan
継続期間: 2004 7 252004 7 28

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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