A multiple-valued reconfigurable VLSI architecture using binary-controlled differential-pair circuits

Xu Bai, Michitaka Kameyama

研究成果: Article査読

3 被引用数 (Scopus)

抄録

This paper presents a fine-grain bit-serial reconfigurable VLSI architecture using multiple-valued switch blocks and binary logic modules. Multiple-valued signaling is utilized to implement a compact switch block. A binary-controlled current-steering technique is introduced, utilizing a programmable three-level differential-pair circuit to implement a high-performance low-power arbitrary two-variable binary function, and increase the noise margins in comparison with the quaternary-controlled differential-pair circuit. A current-source sharing technique between a series-gating differential-pair circuit and a current-mode D-latch is proposed to reduce the current source count and improve the speed. It is demonstrated that the power consumption and the delay of the proposed multiple-valued cell based on the binary-controlled current-steering technique and the current-source-sharing technique are reduced to 63% and 72%, respectively, in comparison with those of a previous multiple-valued cell.

本文言語English
ページ(範囲)1083-1093
ページ数11
ジャーナルIEICE Transactions on Electronics
E96-C
8
DOI
出版ステータスPublished - 2013 8

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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