A multiple-valued logic array VLSI based on two-transistor delta literal circuit and its application to real-time reasoning systems

Takahiro Hanyu, Yasushi Kojima, Tatsuo Higuchi

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

A multiple-valued logic array VLSI for high-speed pattern matching is presented. Both input data and rules are represented by a single multiple-valued digit, so that pattern matching can be described by a multiple-valued delta-literal, in which thresholds correspond to content of a rule. Moreover, a multiple-valued pattern-matching cell can be implemented by only a pair of an NMOS and a PMOS transistors whose threshold voltages are programmed by multiple ion implants. It is demonstrated that the chip area and power dissipation of 8-valued logic array can be reduced to 30% and 50%, respectively, compared with corresponding binary implementation.

本文言語English
ホスト出版物のタイトルProceedings of The International Symposium on Multiple-Valued Logic
出版社Publ by IEEE
ページ16-23
ページ数8
ISBN(印刷版)0818621451
出版ステータスPublished - 1991 5 1
イベントProceedings of the 21st International Symposium on Multiple-Valued Logic - Victoria, BC, Can
継続期間: 1991 5 261991 5 29

出版物シリーズ

名前Proceedings of The International Symposium on Multiple-Valued Logic
ISSN(印刷版)0195-623X

Other

OtherProceedings of the 21st International Symposium on Multiple-Valued Logic
CityVictoria, BC, Can
Period91/5/2691/5/29

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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