A multiple-valued logic array VLSI based on two-transistor delta literal circuit and its application to real-time reasoning systems

A multiple-valued logic array VLSI for high-speed pattern matching is presented. Both input data and rules are represented by a single multiple-valued digit, so that pattern matching can be described by a multiple-valued delta-literal, in which thresholds correspond to content of a rule. Moreover, a multiple-valued pattern-matching cell can be implemented by only a pair of an NMOS and a PMOS transistors whose threshold voltages are programmed by multiple ion implants. It is demonstrated that the chip area and power dissipation of 8-valued logic array can be reduced to 30% and 50%, respectively, compared with corresponding binary implementation.