A Metadata Prefetching Mechanism for Hybrid Memory Architectures

Shunsuke Tsukada, Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi

研究成果: Conference contribution

抄録

A hybrid memory, which is the main memory consisting of two distinct memory devices, is expected to achieve a good balance between high performance and large capacity. However, unlike a traditional memory, the hybrid memory needs the metadata for data management and requires additional access latency for their references. To hide the latency, this paper proposes a metadata prefetching mechanism considering the address differences to control the prefetching. The evaluation results show that the proposed mechanism increases the metadata hit rate in two-thirds of the examined benchmarks and improves IPC by up to 34% and 6% on average.

本文言語English
ホスト出版物のタイトルIEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021 - Proceedings
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9781665415033
DOI
出版ステータスPublished - 2021 4 14
イベント24th IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021 - Virtual, Online, Japan
継続期間: 2021 4 142021 4 16

出版物シリーズ

名前IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021 - Proceedings

Conference

Conference24th IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021
国/地域Japan
CityVirtual, Online
Period21/4/1421/4/16

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ

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