A Metadata Prefetching Mechanism for Hybrid Memory Architectures

Shunsuke Tsukada; Hikaru Takayashiki; Masayuki Sato; Kazuhiko Komatsu; Hiroaki Kobayashi

doi:10.1109/COOLCHIPS52128.2021.9410321

A Metadata Prefetching Mechanism for Hybrid Memory Architectures

Shunsuke Tsukada, Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

A hybrid memory, which is the main memory consisting of two distinct memory devices, is expected to achieve a good balance between high performance and large capacity. However, unlike a traditional memory, the hybrid memory needs the metadata for data management and requires additional access latency for their references. To hide the latency, this paper proposes a metadata prefetching mechanism considering the address differences to control the prefetching. The evaluation results show that the proposed mechanism increases the metadata hit rate in two-thirds of the examined benchmarks and improves IPC by up to 34% and 6% on average.

本文言語	English
ホスト出版物のタイトル	IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021 - Proceedings
出版社	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子版）	9781665415033
DOI	https://doi.org/10.1109/COOLCHIPS52128.2021.9410321
出版ステータス	Published - 2021 4月 14
イベント	24th IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021 - Virtual, Online, Japan 継続期間: 2021 4月 14 → 2021 4月 16

出版物シリーズ

名前	IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021 - Proceedings

Conference

Conference	24th IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021
国/地域	Japan
City	Virtual, Online
Period	21/4/14 → 21/4/16

ASJC Scopus subject areas

ハードウェアとアーキテクチャ

文献へのアクセス

10.1109/COOLCHIPS52128.2021.9410321

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引用スタイル

Tsukada, S., Takayashiki, H., Sato, M., Komatsu, K., & Kobayashi, H. (2021). A Metadata Prefetching Mechanism for Hybrid Memory Architectures. In IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021 - Proceedings [9410321] (IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/COOLCHIPS52128.2021.9410321

A Metadata Prefetching Mechanism for Hybrid Memory Architectures. / Tsukada, Shunsuke; Takayashiki, Hikaru; Sato, Masayuki その他.

IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. 9410321 (IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021 - Proceedings).

研究成果: Conference contribution

Tsukada, S, Takayashiki, H, Sato, M , Komatsu, K & Kobayashi, H 2021, A Metadata Prefetching Mechanism for Hybrid Memory Architectures. in IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021 - Proceedings., 9410321, IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 24th IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021, Virtual, Online, Japan, 21/4/14. https://doi.org/10.1109/COOLCHIPS52128.2021.9410321

Tsukada S, Takayashiki H, Sato M , Komatsu K , Kobayashi H. A Metadata Prefetching Mechanism for Hybrid Memory Architectures. In IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2021. 9410321. (IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021 - Proceedings). doi: 10.1109/COOLCHIPS52128.2021.9410321

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A Metadata Prefetching Mechanism for Hybrid Memory Architectures

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出版物シリーズ

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ASJC Scopus subject areas

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