A low-power Content-Addressable Memory based on clustered-sparse networks

Hooman Jarollahi, Vincent Gripon, Naoya Onizawa, Warren J. Gross

研究成果: Conference contribution

16 被引用数 (Scopus)

抄録

A low-power Content-Addressable Memory (CAM) is introduced employing a new mechanism for associativity between the input tags and the corresponding address of the output data. The proposed architecture is based on a recently developed clustered-sparse network using binary-weighted connections that on-average will eliminate most of the parallel comparisons performed during a search. Therefore, the dynamic energy consumption of the proposed design is significantly lower compared to that of a conventional low-power CAM design. Given an input tag, the proposed architecture computes a few possibilities for the location of the matched tag and performs the comparisons on them to locate a single valid match. A 0.13μm CMOS technology was used for simulation purposes. The energy consumption and the search delay of the proposed design are 9.5%, and 30.4% of that of the conventional NAND architecture respectively with a 3.4% higher number of transistors.

本文言語English
ホスト出版物のタイトルASAP 2013 - Proceedings of the 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors
ページ305-308
ページ数4
DOI
出版ステータスPublished - 2013
外部発表はい
イベント2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2013 - Washington, DC, United States
継続期間: 2013 6 52013 6 7

出版物シリーズ

名前Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
ISSN(印刷版)1063-6862

Conference

Conference2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2013
CountryUnited States
CityWashington, DC
Period13/6/513/6/7

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Networks and Communications

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