A high output resistance 1.2-V VDD current mirror with deep submicron vertical mosfets

Satoru Tanoi, Tetsuo Endoh

研究成果: Article査読

1 被引用数 (Scopus)

抄録

A low VDD current mirror with deep sub-micron vertical MOSFETs is presented. The keys are new bias circuits to reduce both the minimum VDD for the operation and the sensitivity of the output current on VDD. In the simulation, our circuits reduce the minimum VDD by about 17% and the VDD sensitivity by one order both from those of the conventional. In the simulation with 90 nm φ vertical MOSFET approximate models, our circuit shows about 4MΩ output resistance at 1.2-V VDD with the small temperature dependence, which is about six times as large as that with planar MOSFETs.

本文言語English
ページ(範囲)423-430
ページ数8
ジャーナルIEICE Transactions on Electronics
E97-C
5
DOI
出版ステータスPublished - 2014 5

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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