A nonvolatile multi-core associative coprocessor based on the MRAM is developed with open-end design, which achieves the higher power efficiency maintaining the high circuit density, full adaptivity and high-speed at the same time. This proposed coprocessor is proposed applicable for searching nearest pattern from the large-scale normal/pre-clustered data sets. An inter-core pipeline operation scheme is implemented, which absorbs the delay of in-core time-domain minimum searching to ensure the high-speed and flexibly extends the coprocessor by increasing the core count. A self-optimized power gating scheme is also employed, which minimizes the operation power and further reduces it when the cluster number (K) becomes larger. The prototype chip with 12-core is designed and fabricated under 90 nm CMOS/70 nm perpendicular-MTJ hybrid technology, and the chip operation at 100 MHz is demonstrated by measurement results. The average operation power is only 68 μW @K = 24, and more than 40-time higher power efficiency is achieved comparing to the latest conventional researches.
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