A fast hardware/software co-verification method for System-On-a-Chip by using a C/C++ simulator and FPGA emulator with shared register communication

Yuichi Nakamura, Kouhei Hosokawa, Ichiro Kuroda, Ko Yoshikawa, Takeshi Yoshimura

研究成果: Conference article査読

55 被引用数 (Scopus)

抄録

This paper describes a new hardware/software co-verification method for System-On-a-Chip, based on the integration of a C/C++ simulator and an inexpensive FPGA emulator. Communication between the simulator and emulator occurs via a flexible interface based on shared communication registers. This method enables easy debugging, rich portability, and high verification speed, at a low cost. We describe the application of this environment to the verification of three different complex commercial SoCs, supporting concurrent hardware and embedded software development. In these projects, our verification methodology was used to perform complete system verification at 0.2-1.1 MHz, while supporting full graphical interface functions such as "waveform" or "signal dump" viewers, and debugging functions such as "step" or "break".

本文言語English
ページ(範囲)299-304
ページ数6
ジャーナルProceedings - Design Automation Conference
DOI
出版ステータスPublished - 2004
外部発表はい
イベントProceedings of the 41st Design Automation Conference - San Diego, CA, United States
継続期間: 2004 6 72004 6 11

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 制御およびシステム工学

フィンガープリント

「A fast hardware/software co-verification method for System-On-a-Chip by using a C/C++ simulator and FPGA emulator with shared register communication」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル