A dynamically reconfigurable SIMD processor for a vision chip

Takashi Komuro, Shingo Kagami, Masatoshi Ishikawa

研究成果: Article査読

110 被引用数 (Scopus)

抄録

Conventional SIMD image processors are very effective for early visual processing because of their parallelism. However, in performing more advanced processing, they exhibit some problems, such as poor performance in global operations and a tradeoff between flexibility of processing and the number of pixels. This paper shows a new architecture and sample algorithms of a vision chip that has the ability to reconfigure its hardware dynamically by chaining processing elements. A prototype chip with 64 × 64 pixels manufactured using the 0.35-μm CMOS process is also shown.

本文言語English
ページ(範囲)265-268
ページ数4
ジャーナルIEEE Journal of Solid-State Circuits
39
1
DOI
出版ステータスPublished - 2004 1
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

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