A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing

Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno, Tadahiko Sugibayashi

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

A delay circuit using four-terminal magnetic-random-access-memory (MRAM) devices was designed for power-efficient time-domain signal processing. A cell area of 6.4 μm2 was obtained using 90-nm CMOS/MRAM technologies. The basic operations to both store the data and control the delay time were confirmed on the fabricated test chips. In addition, we proposed a power-efficient neuromorphic core using the delay circuit.

本文言語English
ホスト出版物のタイトル2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
出版社Institute of Electrical and Electronics Engineers Inc.
ページ1588-1591
ページ数4
ISBN(印刷版)9781479934324
DOI
出版ステータスPublished - 2014 1 1
イベント2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia
継続期間: 2014 6 12014 6 5

出版物シリーズ

名前Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(印刷版)0271-4310

Other

Other2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
国/地域Australia
CityMelbourne, VIC
Period14/6/114/6/5

ASJC Scopus subject areas

  • 電子工学および電気工学

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