A column-parallel hybrid analog-to-digital converter using successive-approximation-register and single-slope architectures with error correction for complementary metal oxide silicon image sensors

Tsung Ling Li, Shin Sakai, Shun Kawada, Yasuyuki Goda, Shunichi Wakashima, Rihito Kuroda, Shigetoshi Sugawa

研究成果: Article査読

1 被引用数 (Scopus)

抄録

In this paper, a column-parallel hybrid analog-to-digital converter (ADC) architecture taking the advantages of both successive-approximationregister (SAR) and single-slope (SS) architectures has been developed for CMOS image sensors. The proposed architecture achieves high conversion speed and low power consumption without requiring a high clock frequency and a large number of capacitors. Moreover, an error correction methodology has been presented to calibrate capacitance mismatches in a SAR capacitor array for linearity improvement. An 11-bit hybrid prototype ADC has been implemented in a 0.18-m 1-poly 5-metal standard CMOS process. The conversion time is 1.225 s with a maximum operation clock frequency of 40 MHz and it consumes 48 W. With the proposed error correction, the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.40/0:44 least significant bit (LSB) and +1.21/1:12 LSB, respectively.

本文言語English
論文番号04CE04
ジャーナルJapanese journal of applied physics
52
4 PART 2
DOI
出版ステータスPublished - 2013 4 1

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)

フィンガープリント 「A column-parallel hybrid analog-to-digital converter using successive-approximation-register and single-slope architectures with error correction for complementary metal oxide silicon image sensors」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル