A Code Selection Mechanism Using Deep Learning

Hang Cui, Shoichi Hirasawa, Hiroyuki Takizawa, Hiroaki Kobayashi

研究成果: Conference contribution

7 被引用数 (Scopus)

抄録

Sparse Matrix-Vector multiplication (SpMV) is a computational kernel widely used in many applications. There are many different implementations using different processors and algorithms for SpMV. The performances of different SpMV implementations are quite different, and it is basically difficult to choose the implementation that has the best performance for a given sparse matrix and a given platform without performance profiling. This work presents a prototype implementation of an effective machine learning system for SpMV code selection best suited for a given matrix. Instead of using predefined features of a matrix for performance prediction, a feature image and a deep learning network are used to map each sparse matrix to the implementation that has the best performance in advance of the execution. The performance gain by the mechanism is evaluated by using a machine learning method for predicting the best SpMV implementation. According to our evaluation, the proposed mechanism can select an optimal or suboptimal implementation in most cases, though the prediction is not perfect. These results demonstrate the feasibility that the proposed machine learning approach can capture underlying features of an input sparse matrix useful for SpMV code selection.

本文言語English
ホスト出版物のタイトルProceedings - IEEE 10th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016
出版社Institute of Electrical and Electronics Engineers Inc.
ページ385-392
ページ数8
ISBN(電子版)9781509035304
DOI
出版ステータスPublished - 2016 12 5
イベント10th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016 - Lyon, France
継続期間: 2016 9 212016 9 23

出版物シリーズ

名前Proceedings - IEEE 10th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016

Other

Other10th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016
CountryFrance
CityLyon
Period16/9/2116/9/23

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture

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