A 600-μW ultra-low-power associative processor for image pattern recognition employing magnetic tunnel junction-based nonvolatile memories with autonomic intelligent power-gating scheme

研究成果: Article査読

11 被引用数 (Scopus)

抄録

A novel associative processor using magnetic tunnel junction (MTJ)-based nonvolatile memories has been proposed and fabricated under a 90 nm CMOS/70nm perpendicular-MTJ (p-MTJ) hybrid process for achieving the exceptionally low-power performance of image pattern recognition. A four-transistor 2-MTJ (4T-2MTJ) spin transfer torque magnetoresistive random access memory was adopted to completely eliminate the standby power. A self-directed intelligent power-gating (IPG) scheme specialized for this associative processor is employed to optimize the operation power by only autonomously activating currently accessed memory cells. The operations of a prototype chip at 20MHz are demonstrated by measurement. The proposed processor can successfully carry out single texture pattern matching within 6.5 μs using 128-dimension bag-offeature patterns, and the measured average operation power of the entire processor core is only 600μW. Compared with the twin chip designed with 6T static random access memory, 91.2% power reductions are achieved. More than 88.0% power reductions are obtained compared with the latest associative memories. The further power performance analysis is discussed in detail, which verifies the special superiority of the proposed processor in power consumption for large-capacity memory-based VLSI systems.

本文言語English
論文番号04EF15
ジャーナルJapanese journal of applied physics
55
4
DOI
出版ステータスPublished - 2016 4 1

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)

フィンガープリント 「A 600-μW ultra-low-power associative processor for image pattern recognition employing magnetic tunnel junction-based nonvolatile memories with autonomic intelligent power-gating scheme」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル