TY - JOUR
T1 - A 600-μW ultra-low-power associative processor for image pattern recognition employing magnetic tunnel junction-based nonvolatile memories with autonomic intelligent power-gating scheme
AU - Ma, Yitao
AU - Miura, Sadahiko
AU - Honjo, Hiroaki
AU - Ikeda, Shoji
AU - Hanyu, Takahiro
AU - Ohno, Hideo
AU - Endoh, Tetsuo
N1 - Publisher Copyright:
© 2016 The Japan Society of Applied Physics.
PY - 2016/4
Y1 - 2016/4
N2 - A novel associative processor using magnetic tunnel junction (MTJ)-based nonvolatile memories has been proposed and fabricated under a 90 nm CMOS/70nm perpendicular-MTJ (p-MTJ) hybrid process for achieving the exceptionally low-power performance of image pattern recognition. A four-transistor 2-MTJ (4T-2MTJ) spin transfer torque magnetoresistive random access memory was adopted to completely eliminate the standby power. A self-directed intelligent power-gating (IPG) scheme specialized for this associative processor is employed to optimize the operation power by only autonomously activating currently accessed memory cells. The operations of a prototype chip at 20MHz are demonstrated by measurement. The proposed processor can successfully carry out single texture pattern matching within 6.5 μs using 128-dimension bag-offeature patterns, and the measured average operation power of the entire processor core is only 600μW. Compared with the twin chip designed with 6T static random access memory, 91.2% power reductions are achieved. More than 88.0% power reductions are obtained compared with the latest associative memories. The further power performance analysis is discussed in detail, which verifies the special superiority of the proposed processor in power consumption for large-capacity memory-based VLSI systems.
AB - A novel associative processor using magnetic tunnel junction (MTJ)-based nonvolatile memories has been proposed and fabricated under a 90 nm CMOS/70nm perpendicular-MTJ (p-MTJ) hybrid process for achieving the exceptionally low-power performance of image pattern recognition. A four-transistor 2-MTJ (4T-2MTJ) spin transfer torque magnetoresistive random access memory was adopted to completely eliminate the standby power. A self-directed intelligent power-gating (IPG) scheme specialized for this associative processor is employed to optimize the operation power by only autonomously activating currently accessed memory cells. The operations of a prototype chip at 20MHz are demonstrated by measurement. The proposed processor can successfully carry out single texture pattern matching within 6.5 μs using 128-dimension bag-offeature patterns, and the measured average operation power of the entire processor core is only 600μW. Compared with the twin chip designed with 6T static random access memory, 91.2% power reductions are achieved. More than 88.0% power reductions are obtained compared with the latest associative memories. The further power performance analysis is discussed in detail, which verifies the special superiority of the proposed processor in power consumption for large-capacity memory-based VLSI systems.
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U2 - 10.7567/JJAP.55.04EF15
DO - 10.7567/JJAP.55.04EF15
M3 - Article
AN - SCOPUS:84963674163
VL - 55
JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
SN - 0021-4922
IS - 4
M1 - 04EF15
ER -