A 500-MHz MRAM macro is developed using a 0.15-μm CMOS process and a newly developed MRAM process. The macro is designed using a 20.17-μm 2 5-transistor 2-magnetic tunnel junction (5T2MTJ) cell that has individual ports for writing and reading. An access time of less than 2 ns was obtained by employing a hierarchically-divided read bit line (RBL) and a high pre-charge sensing scheme. The operation speed is the highest among MRAMs that have been reported. This MRAM macro can coexist with the more area-effective 2TlMTJ-cell-based MRAM macro in SoCs.