A 500-MHz MRAM macro for high-performance SoCs

Noboru Sakimura, Ryusuke Nebashi, Hiroaki Honjo, Shinsaku Saito, Yuko Kato, Tadahiko Sugibayashi

研究成果: Conference contribution

10 被引用数 (Scopus)

抄録

A 500-MHz MRAM macro is developed using a 0.15-μm CMOS process and a newly developed MRAM process. The macro is designed using a 20.17-μm 2 5-transistor 2-magnetic tunnel junction (5T2MTJ) cell that has individual ports for writing and reading. An access time of less than 2 ns was obtained by employing a hierarchically-divided read bit line (RBL) and a high pre-charge sensing scheme. The operation speed is the highest among MRAMs that have been reported. This MRAM macro can coexist with the more area-effective 2TlMTJ-cell-based MRAM macro in SoCs.

本文言語English
ホスト出版物のタイトルProceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
ページ261-264
ページ数4
DOI
出版ステータスPublished - 2008 12 1
外部発表はい
イベント2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 - Fukuoka, Japan
継続期間: 2008 11 32008 11 5

出版物シリーズ

名前Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Other

Other2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
国/地域Japan
CityFukuoka
Period08/11/308/11/5

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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