A 35-GHz 20- μm2 self-aligned PNP technology for ultra-high-speed high-density complementary bipolar ULSIs

Katsuyoslii Washio, K. Hiromi Shimamoto, Toliru Nakainura

研究成果: Conference contribution

6 被引用数 (Scopus)

抄録

An ultra-high-speed high-density self-aligned pup technology for complementary bipolar ULSIs has been developed which is fully compatible wilh the npn process. Low sheet-resistance p+ buried layer and extrinsic n+ polysilicon layer with U-grooved isolation enable transistor size to be sealed down to about 20 μm2. A shallow emitter junction depth of 45 nm and narrow hase width of 30 nm improve maximum cutoff frequency to 35 GHz The power dissipation of pnp pulldown complementary emitter-follower ECL circuit for the loaded ease is calculated lo be reduced to 1/5 compared with the conventional ECL circuit.

本文言語English
ホスト出版物のタイトル1992 Symposium on VLSI Technology - Digest of Technical Papers, VLSI Technology 1992
出版社Institute of Electrical and Electronics Engineers Inc.
ページ64-65
ページ数2
ISBN(電子版)0780306988
DOI
出版ステータスPublished - 1992
外部発表はい
イベント1992 Symposium on VLSI Technology - Digest of Technical Papers, VLSI Technology 1992 - Seattle, United States
継続期間: 1992 6 21992 6 4

出版物シリーズ

名前Digest of Technical Papers - Symposium on VLSI Technology
1992-June
ISSN(印刷版)0743-1562

Conference

Conference1992 Symposium on VLSI Technology - Digest of Technical Papers, VLSI Technology 1992
CountryUnited States
CitySeattle
Period92/6/292/6/4

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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