A 64-Mb DRAM with a 30-ns access time and 19.48mm x 9.55-mm die size has been developed. For reducing inter-bit-line coupling noise, the DRAM features a latched-sense, shared-sense circuit with open bit-line readout and folded bit-line rewrite operations. To reduce test costs and increase chip reliability, it has been equipped with built-in self-test and self-repair (BIST and BISR) circuits that use spare SRAM cells.
ASJC Scopus subject areas
- Electrical and Electronic Engineering