A 30-ns 64-Mb DRAM with Built-in Self-Test and Self-Repair Function

Akira Tanabe, Toshio Takeshima, Hiroki Koike, Yoshiharu Aimoto, Masahide Takada, Toshiyuki Ishijima, Naoki Kasai, Hiromitsu Hada, Kentaro Shibahara, Takemitsu Kunio, Takaho Tanigawa, Takanori Saeki, Masato Sakao, Hidenobu Miyamoto, Hiroshi Nozue, Shuichi Ohya, Tatsunori Murotani, Kuniaki Koyama, Takashi Okuda

研究成果: Article査読

50 被引用数 (Scopus)

抄録

A 64-Mb DRAM with a 30-ns access time and 19.48mm x 9.55-mm die size has been developed. For reducing inter-bit-line coupling noise, the DRAM features a latched-sense, shared-sense circuit with open bit-line readout and folded bit-line rewrite operations. To reduce test costs and increase chip reliability, it has been equipped with built-in self-test and self-repair (BIST and BISR) circuits that use spare SRAM cells.

本文言語English
ページ(範囲)1525-1533
ページ数9
ジャーナルIEEE Journal of Solid-State Circuits
27
11
DOI
出版ステータスPublished - 1992 11
外部発表はい

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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