A 3-ns Range, 8-ps Resolution, Timing Generator LSI Utilizing Si Bipolar Gate Array

Tai Ichi Otsuji, Naoaki Narumi

研究成果: Article査読

16 被引用数 (Scopus)

抄録

A 3-ns range, 8-ps resolution, timing generator LSI has been realized by using Si bipolar gate arrays. By adopting a redundant weighted delay-unit matrix based on a process-insensitive polynomial formulation, ±2-ps linearity error has been attained at input clock rates of up to 700 MHz. Thermal noise and interconnection crosstalk have been quantitatively investigated as critical factors causing timing error. By adopting the results to the circuit and layout design, thermal jitter and systematic timing error due to crosstalk have been successfully suppressed to less than 8 and ±5 ps, respectively.

本文言語English
ページ(範囲)806-811
ページ数6
ジャーナルIEEE Journal of Solid-State Circuits
26
5
DOI
出版ステータスPublished - 1991 5月
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

フィンガープリント

「A 3-ns Range, 8-ps Resolution, Timing Generator LSI Utilizing Si Bipolar Gate Array」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル