A 1.88ns 54×54-bit multiplier in 0.18μm CMOS based on multiple-valued differential-pair circuitry

Akira Mochizuki, Takahiro Hanyu

研究成果: Paper査読

13 被引用数 (Scopus)

抄録

This paper presents a new 54 × 54-bit multiplier using fully differential-pair circuits (DPCs). The DPC is a key component in maintaining an input signal-voltage swing of 0.2V while providing a large current-driving capability. The combination of the DPC and the multi-level current-mode linear summation makes critical-path delay and transistor counts reduced, which achieves 1.88ns latency with 74.2mW from a 1.8V supply on a 0.85mm2 die. It is also discussed about the efficiency of the DPCs for crosstalk noise reduction.

本文言語English
ページ264-267
ページ数4
DOI
出版ステータスPublished - 2005 12月 1
イベント2005 Symposium on VLSI Circuits - Kyoto, Japan
継続期間: 2005 6月 162005 6月 18

Other

Other2005 Symposium on VLSI Circuits
国/地域Japan
CityKyoto
Period05/6/1605/6/18

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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