A 0.8dB insertion-loss, 23dB isolation, 17.4dBm power-handling, 5GHz transmit/receive CMOS switch

Takahiro Ohnakado, Satoshi Yamakawa, Takaaki Murakami, Akihiko Furukawa, Kazuyasu Nishikawa, Eiji Taniguchi, Hiroomi Ueda, Masayoshi Ono, Jun Tomisawa, Yoshikazu Yoneda, Yasushi Hashizume, Kazuyuki Sugahara, Noriharu Suematsu, Tatsuo Oomori

研究成果: Paper査読

6 被引用数 (Scopus)

抄録

The highest performance to date of any switch using a CMOS process, of a 0.8dB insertion-loss, 23dB isolation and 17.4dBm power-handling capability at 5GHz, is accomplished with an optimized single-pole double-throw (SPDT) transmit/receive (T/R) switch using Depletion-layer-Extended Transistors (DETs) in a 0.18μm CMOS process. The effects of junction capacitance decrease and substrate resistance increase in the DET, the adoption of low-loss shielded-pads, and several layout optimizations, lead to the realization of this low insertion-loss. Moreover, the combined effect of the adoption of the source/drain DC biasing scheme and the high substrate resistance in the DET contributes to the high power-handling capability.

本文言語English
ページ229-232
ページ数4
出版ステータスPublished - 2003 8月 25
外部発表はい
イベント2003 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium - Philadelphia, PA, United States
継続期間: 2003 6月 82003 6月 10

Other

Other2003 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium
国/地域United States
CityPhiladelphia, PA
Period03/6/803/6/10

ASJC Scopus subject areas

  • 工学(全般)

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