We have successfully developed a 0.602 um2 nestled 'Chain' FeRAM cell technology for 64Mbit FeRAM. In the 'Chain' FeRAM, a pair of capacitors on a same node can be nestled close to each other. A combination of a one mask etching process of ferro-electric capacitors and the nestled structure drastically scaled down the cell size to 0.602um2. The cell size was reduced to 32% of previous work. Signal window of 600mV was obtained by the nestled 'Chain' FeRAM structure after full integration of three-metal CMOS technology.
|ジャーナル||Digest of Technical Papers - Symposium on VLSI Technology|
|出版ステータス||Published - 2004|
|イベント||2004 Symposium on VLSI Technology - Digest of Technical Papers - Honolulu, HI, United States|
継続期間: 2004 6 15 → 2004 6 17
ASJC Scopus subject areas