A 0.602 um2 nestled Chain cell structure formed by one mask etching process for 64 Mbit FeRAM

H. Kanaya, K. Tomioka, T. Matsushita, M. Omura, T. Ozaki, Y. Kumura, Y. Shimojo, T. Morimoto, O. Hidaka, S. Shuto, H. Koyama, Y. Yamada, K. Osari, N. Tokoh, F. Fujisaki, N. Iwabuchi, N. Yamaguchi, T. Watanabe, M. Yabuki, H. ShinomiyaN. Watanabe, E. Itoh, T. Tsuchiya, K. Yamakawa, K. Natori, S. Yamazaki, K. Nakazawa, D. Takashima, S. Shiratake, S. Ohtsuki, Y. Oowaki, I. Kunishima, A. Nitayama

研究成果: Conference article査読

19 被引用数 (Scopus)

抄録

We have successfully developed a 0.602 um2 nestled 'Chain' FeRAM cell technology for 64Mbit FeRAM. In the 'Chain' FeRAM, a pair of capacitors on a same node can be nestled close to each other. A combination of a one mask etching process of ferro-electric capacitors and the nestled structure drastically scaled down the cell size to 0.602um2. The cell size was reduced to 32% of previous work. Signal window of 600mV was obtained by the nestled 'Chain' FeRAM structure after full integration of three-metal CMOS technology.

本文言語English
ページ(範囲)150-151
ページ数2
ジャーナルDigest of Technical Papers - Symposium on VLSI Technology
出版ステータスPublished - 2004
イベント2004 Symposium on VLSI Technology - Digest of Technical Papers - Honolulu, HI, United States
継続期間: 2004 6 152004 6 17

ASJC Scopus subject areas

  • 電子工学および電気工学

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