80nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process

H. Sayama, Y. Nishida, H. Oda, J. Tsuchimoto, H. Umeda, A. Teramoto, K. Eikyu, Y. Inoue, M. Inuishi

研究成果: Conference article査読

11 被引用数 (Scopus)

抄録

The fabrication of high drive current CMOSFET with 80 nanometer gate length was discussed. Short channel effects (SCE) and parasitic resistance in sub-0.1 micrometer CMOS were improved with the help of double offset-implanted sourse drain extension and silicon nitride deposition. A drive current of 830/400 micro ampere per nanometer with 2.5 nanometer gate insulator was achieved under 1 nanoampere per micrometer offstate leakage at 1.5V operation with 80 nanometer gate length.

本文言語English
ページ(範囲)239-242
ページ数4
ジャーナルTechnical Digest - International Electron Devices Meeting
出版ステータスPublished - 2000 12 1
外部発表はい
イベント2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States
継続期間: 2000 12 102000 12 13

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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