A 67-GHz 1/4 static frequency divider using 0.2-μm self-aligned selective-epitaxial-growth SiGe heterqjunction bipolar transistors, with a 122-GHz cutoff frequency, a 163-GHz maximum oscillation frequency, and an average emitter coupled logic gate delay time of 5.65 ps, was developed. The pretracking master-slave toggle flip-flop (MS-TFF) of the divider increases the maximum operating frequency to about 15% higher than that of a conventional MS-TFF, yet the power consumption of the divider is 175 mW, which is 1/5 that of comparable dividers, at a supply voltage of -5.2 V. Index Terms -.
|ジャーナル||IEEE Transactions on Microwave Theory and Techniques|
|出版ステータス||Published - 2001|
|イベント||2000 Radio-Frequency Integrated Circuits (RFIC) Conference and Automatic Radio Frequency Techniques Group (ARFTG) Meeting - Boston, MA, United States|
継続期間: 2000 6月 12 → 2000 6月 16
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