A high-speed silicon bipolar transistor structure and very-high-speed emitter coupled logic (ECL) circuits are demonstrated. The circuits were fabricated with an advanced sidewall contact structure (SICOS) technology featuring emitter shallow profile and very shallow graft base regions. Minimum gate delay of 63 ps/G at FI equals 1 and 79 ps/G at FI equals 3 were obtained with advanced SICOS technology.
|ジャーナル||Technical Digest - International Electron Devices Meeting|
|出版ステータス||Published - 1986|
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
- Materials Chemistry