63 PS ECL CIRCUITS USING ADVANCED SICOS TECHNOLOGY.

Tohru Nakamura, Kiyoji Ikeda, Kazuo Nakazato, Katsuyoshi Washio, Mitsuo Namba, Tetsuya Hayashida

研究成果: Conference article査読

10 被引用数 (Scopus)

抄録

A high-speed silicon bipolar transistor structure and very-high-speed emitter coupled logic (ECL) circuits are demonstrated. The circuits were fabricated with an advanced sidewall contact structure (SICOS) technology featuring emitter shallow profile and very shallow graft base regions. Minimum gate delay of 63 ps/G at FI equals 1 and 79 ps/G at FI equals 3 were obtained with advanced SICOS technology.

本文言語English
ページ(範囲)472-475
ページ数4
ジャーナルTechnical Digest - International Electron Devices Meeting
DOI
出版ステータスPublished - 1986
外部発表はい

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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