4.8GHz CMOS frequency multiplier with subharmonic pulse-injection locking

Kyoya Takano, Mizuki Motoyoshi, Minoru Fujishima

研究成果: Conference contribution

28 被引用数 (Scopus)

抄録

To realize low-power wireless transceivers, it is required to improve the performance of a frequency synthesizer, which is typically used as a frequency multiplier and is composed of a phase-locked loop (PLL). However a general PLL consumes much power and occupies a large area. To improve the frequency multiplier, we propose a pulse-injection-locked frequency multiplier (PILFM), in which spurious signals are suppressed by using a pulse input signal. An injection-locked oscillator (ILO) in a PILFM was fabricated by a 0.18mm 1P5M CMOS process. The core size was 10.8mm x 10.5mm. The power consumption of the ILO is 9.6mW at 250MHz, and 1.47mW at 4.8GHz. The phase noise is -108dBc/Hz at 1MHz offset. For a ten-times frequency multiplier, output phase noise is 10dB larger than the input phase noise below 10kHz offset, which is the theoretical limit.

本文言語English
ホスト出版物のタイトル2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
ページ336-339
ページ数4
DOI
出版ステータスPublished - 2007 12 1
外部発表はい
イベント2007 IEEE Asian Solid-State Circuits Conference, A-SSCC - Jeju, Korea, Republic of
継続期間: 2007 11 122007 11 14

出版物シリーズ

名前2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Other

Other2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
国/地域Korea, Republic of
CityJeju
Period07/11/1207/11/14

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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