40 nm 1T-1MTJ 128 Mb STT-MRAM with Novel Averaged Reference Voltage Generator Based on Detailed Analysis of Scaled-Down Memory Cell Array Design

Hiroki Koike, Takaho Tanigawa, Toshinari Watanabe, Takashi Nasuno, Yasuo Noguchi, Mitsuo Yasuhira, Toru Yoshiduka, Yitao Ma, Hiroaki Honjo, Koichi Nishioka, Sadahiko Miura, Hirofumi Inoue, Shoji Ikeda, Tetsuo Endoh

研究成果: Article査読

抄録

The development of STT-MRAM technology is currently in progress and has been successively disclosed by major LSI vendors recently. In order to advance STT-MRAM technology and expand its areas of application, challenges relative to further device scaling need to be addressed. In this study, an increased wiring resistance in a deep sub-100 nm process by which the read operation yield is degraded was analyzed. The yield degradation was quantified by analyzing the conventional cell array using Monte-Carlo SPICE simulations. A new circuit was proposed to decrease the fail bit rate by an averaged reference voltage ( V ) generator. The simulated results indicated that the new V generator improved the fail bit rate by 1 order of magnitude compared to the conventional array. To demonstrate the circuit operation, a 128 Mb STT-MRAM chip was designed and fabricated using 40 nm CMOS and 37 nm MTJ technologies. For the first time, the chip measurements successfully demonstrated the operation of the proposed device-variation tolerant array architecture with the averaged V generator, presenting a 30 ns read access time.

本文言語English
論文番号9260242
ジャーナルIEEE Transactions on Magnetics
57
3
DOI
出版ステータスPublished - 2021 3

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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