4-bit SFQ multiplier based on booth encoder

Ryosuke Nakamoto, Sakae Sakuraba, Takeshi Onomi, Shigeo Sato, Koji Nakajima

研究成果: Article査読

6 被引用数 (Scopus)

抄録

We have designed a 2-bit Booth encoder with Josephson Transmission Lines (JTLs) and Passive Transmission Lines (PTLs) by using cell-based techniques and tools. The Booth encoding method is one of the algorithms to obtain partial products. With this method, the number of partial products decreases down to the half compared to the AND array method. We have fabricated a test chip for a multiplier with a 2-bit Booth encoder with JTLs and PTLs. It has a processing frequency of 20 GHz with the bias margin ±25%. The frequency of this circuit increases up to 45 GHz with the bias voltage by 25% increased from the design voltage. The circuit area of the multiplier designed with the Booth encoder method is compared to that designed with the AND array method.

本文言語English
論文番号5680955
ページ(範囲)852-855
ページ数4
ジャーナルIEEE Transactions on Applied Superconductivity
21
3 PART 1
DOI
出版ステータスPublished - 2011 6

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 凝縮系物理学
  • 電子工学および電気工学

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