3D memory chip stacking by multi-layer self-assembly technology

Takafumi Fukushima, Jichoru Be, M. Murugesan, H. Y. Son, M. S. Suh, K. Y. Byun, N. S. Kim, Kanuku Ri, Mitsumasa Koyanagi

研究成果: Conference contribution

6 被引用数 (Scopus)

抄録

Multi-layer 3D chip stacking by a surface-tension-driven self-assembly technique is demonstrated. After multi-layer self-assembly, memory chips having Cu-SnAg μbump and Cu-TSVs are bonded on a substrate by thermal compression to confirm electrical joining between them. In addition, we investigate the impacts of wetting properties of chip/substrate surfaces, μbump shapes, and μbump layout on alignment accuracies of self-assembly. Good electrical characteristics are obtained from the TSV-μbump daisy chains in the stacked memory chips.

本文言語English
ホスト出版物のタイトル2013 IEEE International 3D Systems Integration Conference, 3DIC 2013
DOI
出版ステータスPublished - 2013 12 1
イベント2013 IEEE International 3D Systems Integration Conference, 3DIC 2013 - San Francisco, CA, United States
継続期間: 2013 10 22013 10 4

出版物シリーズ

名前2013 IEEE International 3D Systems Integration Conference, 3DIC 2013

Other

Other2013 IEEE International 3D Systems Integration Conference, 3DIC 2013
CountryUnited States
CitySan Francisco, CA
Period13/10/213/10/4

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Computer Science Applications

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