3D LSI and reliability

Mitsumasa Koyanagi

研究成果: Conference contribution

抄録

Three-dimensional (3D) integration technologies including a new 3D heterogeneous integration of super-chip are described. In addition, reliability issues in these 3D LSIs such as mechanical stresses induced by through-silicon vias (TSVs) and metal microbumps and Cu contamination in thinned wafers are discussed. Furthermore, design and test methodologies to improve the reliability of 3D LSIs are discussed.

本文言語English
ホスト出版物のタイトル18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2011
DOI
出版ステータスPublished - 2011 9 15
イベント18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2011 - Incheon, Korea, Republic of
継続期間: 2011 7 42011 7 7

出版物シリーズ

名前Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Other

Other18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2011
CountryKorea, Republic of
CityIncheon
Period11/7/411/7/7

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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