3D integration technology and reliability

Three-dimensional (3D) integration technologies including a new 3D heterogeneous integration of super-chip are described. In addition, reliability issues in these 3D LSIs such as mechanical stresses induced by through-silicon vias (TSVs) and metal microbumps and Cu contamination in thinned wafers are discussed. Cu TSVs with the diameter of 20μm induced the maximum compressive stress of ∼1 GPa at the silicon substrate adjacent to them after annealed at 300°C for 30 min. Mechanical strain/stress and crystal defects were produced in extremely thin wafers (thickness ∼10μm) of 3D LSIs not only during wafer thinning, but also after wafer bonding using fine-pitch, high-density metal microbumps and curing. The influence of Cu contamination at the back surface of the thinned wafer has been evaluated by C-t analysis. C-t curves measured in MOS capacitors without IG layer and EG layer were seriously degraded after annealing even at 200°C whereas the C-t curves exhibited only a little change even after annealing up to 350 min at 300°C. It was revealed that the generation lifetime of minority carrier is significantly reduced by the Cu contamination.