32 multiplied by 32-BIT MULTIPLIER USING MULTIPLE-VALUED MOS CURRENT-MODE CIRCUITS.

Shoji Kawahito, Michitaka Kameyama, Tatsuo Higuchi, Haruyasu Yamada

研究成果: Article査読

10 被引用数 (Scopus)

抄録

A 32 multiplied by 32-bit multiplier using multiple-valued current-mode circuits has been fabricated in 2- mu m CMOS technology. For the multiplier based on the radix-4 signed-digit (SD) number system, 32 multiplied by 32-bit two's complement multiplication can be performed with only three-stage SD full adders using a binary-tree addition scheme. The chip contains about 23,600 transistors and the effective multiplier size is about 3. 2 multiplied by 5. 2 mm**2, which is half that of the corresponding binary CMOS multiplier. The multiply time is less than 59 ns. The performance is considered comparable to that of the fastest binary multiplier reported.

本文言語English
ジャーナルIEEE Journal of Solid-State Circuits
23
1
出版ステータスPublished - 1987 2月 1

ASJC Scopus subject areas

  • 電子工学および電気工学

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