A 32 multiplied by 32-bit multiplier using multiple-valued current-mode circuits has been fabricated in 2- mu m CMOS technology. For the multiplier based on the radix-4 signed-digit (SD) number system, 32 multiplied by 32-bit two's complement multiplication can be performed with only three-stage SD full adders using a binary-tree addition scheme. The chip contains about 23,600 transistors and the effective multiplier size is about 3. 2 multiplied by 5. 2 mm**2, which is half that of the corresponding binary CMOS multiplier. The multiply time is less than 59 ns. The performance is considered comparable to that of the fastest binary multiplier reported.
|ジャーナル||IEEE Journal of Solid-State Circuits|
|出版ステータス||Published - 1987 2月 1|
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