32-Mb 2T1R SPRAM with localized bi-directional write driver and '1'/'0' dual-array equalized reference cell

R. Takemura, T. Kawahara, K. Miura, H. Yamamoto, J. Hayakawa, N. Matsuzaki, K. Ono, Michihiko Yamanouchi, K. Ito, H. Takahashi, S. Ikeda, H. Hasegawa, H. Matsuoka, H. Ohno

研究成果: Conference contribution

12 被引用数 (Scopus)

抄録

A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ns at a supply voltage of 1.8 V. The chip was fabricated with 150-nm CMOS and a 100 × 200 nm tunnel magnetoresistive device element. This chip features three ircuit technologies suitable for a large-scale array: 1) a two-transistor, one-resistor (2T1R) type memory cell for achieving a sufficiently large writing current despite the small cell size, 2) a compact read/write separated hierarchy bit/source-line structure with a localized bi-directional write driver for efficiently distributing writing current, and 3) a '1'/'0' dual-array equalized reference cell for stable read operation.

本文言語English
ホスト出版物のタイトル2009 Symposium on VLSI Circuits
ページ84-85
ページ数2
出版ステータスPublished - 2009 11 18
イベント2009 Symposium on VLSI Circuits - Kyoto, Japan
継続期間: 2009 6 162009 6 18

出版物シリーズ

名前IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2009 Symposium on VLSI Circuits
CountryJapan
CityKyoto
Period09/6/1609/6/18

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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