32-Mb 2T1R SPRAM with localized bi-directional write driver and '1'/'0' dual-array equalized reference cell

R. Takemura; T. Kawahara; K. Miura; H. Yamamoto; J. Hayakawa; N. Matsuzaki; K. Ono; Michihiko Yamanouchi; K. Ito; H. Takahashi; S. Ikeda; H. Hasegawa; H. Matsuoka; H. Ohno

32-Mb 2T1R SPRAM with localized bi-directional write driver and '1'/'0' dual-array equalized reference cell

R. Takemura, T. Kawahara, K. Miura, H. Yamamoto, J. Hayakawa, N. Matsuzaki, K. Ono, Michihiko Yamanouchi, K. Ito, H. Takahashi, S. Ikeda, H. Hasegawa, H. Matsuoka, H. Ohno

研究成果: Conference contribution

12 被引用数 (Scopus)

抄録

A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ns at a supply voltage of 1.8 V. The chip was fabricated with 150-nm CMOS and a 100 × 200 nm tunnel magnetoresistive device element. This chip features three ircuit technologies suitable for a large-scale array: 1) a two-transistor, one-resistor (2T1R) type memory cell for achieving a sufficiently large writing current despite the small cell size, 2) a compact read/write separated hierarchy bit/source-line structure with a localized bi-directional write driver for efficiently distributing writing current, and 3) a '1'/'0' dual-array equalized reference cell for stable read operation.

本文言語	English
ホスト出版物のタイトル	2009 Symposium on VLSI Circuits
ページ	84-85
ページ数	2
出版ステータス	Published - 2009 11 18
イベント	2009 Symposium on VLSI Circuits - Kyoto, Japan 継続期間: 2009 6 16 → 2009 6 18

出版物シリーズ

名前	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2009 Symposium on VLSI Circuits
Country	Japan
City	Kyoto
Period	09/6/16 → 09/6/18

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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引用スタイル

Takemura, R., Kawahara, T., Miura, K., Yamamoto, H., Hayakawa, J., Matsuzaki, N., Ono, K., Yamanouchi, M., Ito, K., Takahashi, H., Ikeda, S., Hasegawa, H., Matsuoka, H., & Ohno, H. (2009). 32-Mb 2T1R SPRAM with localized bi-directional write driver and '1'/'0' dual-array equalized reference cell. In 2009 Symposium on VLSI Circuits (pp. 84-85). [5205284] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

32-Mb 2T1R SPRAM with localized bi-directional write driver and '1'/'0' dual-array equalized reference cell. / Takemura, R.; Kawahara, T.; Miura, K.; Yamamoto, H.; Hayakawa, J.; Matsuzaki, N.; Ono, K.; Yamanouchi, Michihiko; Ito, K.; Takahashi, H.; Ikeda, S.; Hasegawa, H.; Matsuoka, H.; Ohno, H.

2009 Symposium on VLSI Circuits. 2009. p. 84-85 5205284 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

研究成果: Conference contribution

Takemura, R, Kawahara, T, Miura, K, Yamamoto, H, Hayakawa, J, Matsuzaki, N, Ono, K, Yamanouchi, M, Ito, K, Takahashi, H, Ikeda, S, Hasegawa, H, Matsuoka, H & Ohno, H 2009, 32-Mb 2T1R SPRAM with localized bi-directional write driver and '1'/'0' dual-array equalized reference cell. in 2009 Symposium on VLSI Circuits., 5205284, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 84-85, 2009 Symposium on VLSI Circuits, Kyoto, Japan, 09/6/16.

Takemura, R. ; Kawahara, T. ; Miura, K. ; Yamamoto, H. ; Hayakawa, J. ; Matsuzaki, N. ; Ono, K. ; Yamanouchi, Michihiko ; Ito, K. ; Takahashi, H. ; Ikeda, S. ; Hasegawa, H. ; Matsuoka, H. ; Ohno, H. / 32-Mb 2T1R SPRAM with localized bi-directional write driver and '1'/'0' dual-array equalized reference cell. 2009 Symposium on VLSI Circuits. 2009. pp. 84-85 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

@inproceedings{48170cea729e4f3e9072f58a2e20e2de,

title = "32-Mb 2T1R SPRAM with localized bi-directional write driver and '1'/'0' dual-array equalized reference cell",

abstract = "A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ns at a supply voltage of 1.8 V. The chip was fabricated with 150-nm CMOS and a 100 × 200 nm tunnel magnetoresistive device element. This chip features three ircuit technologies suitable for a large-scale array: 1) a two-transistor, one-resistor (2T1R) type memory cell for achieving a sufficiently large writing current despite the small cell size, 2) a compact read/write separated hierarchy bit/source-line structure with a localized bi-directional write driver for efficiently distributing writing current, and 3) a '1'/'0' dual-array equalized reference cell for stable read operation.",

author = "R. Takemura and T. Kawahara and K. Miura and H. Yamamoto and J. Hayakawa and N. Matsuzaki and K. Ono and Michihiko Yamanouchi and K. Ito and H. Takahashi and S. Ikeda and H. Hasegawa and H. Matsuoka and H. Ohno",

year = "2009",

month = nov,

day = "18",

language = "English",

isbn = "9784863480018",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

pages = "84--85",

booktitle = "2009 Symposium on VLSI Circuits",

note = "2009 Symposium on VLSI Circuits ; Conference date: 16-06-2009 Through 18-06-2009",

}

TY - GEN

T1 - 32-Mb 2T1R SPRAM with localized bi-directional write driver and '1'/'0' dual-array equalized reference cell

AU - Takemura, R.

AU - Kawahara, T.

AU - Miura, K.

AU - Yamamoto, H.

AU - Hayakawa, J.

AU - Matsuzaki, N.

AU - Ono, K.

AU - Yamanouchi, Michihiko

AU - Ito, K.

AU - Takahashi, H.

AU - Ikeda, S.

AU - Hasegawa, H.

AU - Matsuoka, H.

AU - Ohno, H.

PY - 2009/11/18

Y1 - 2009/11/18

N2 - A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ns at a supply voltage of 1.8 V. The chip was fabricated with 150-nm CMOS and a 100 × 200 nm tunnel magnetoresistive device element. This chip features three ircuit technologies suitable for a large-scale array: 1) a two-transistor, one-resistor (2T1R) type memory cell for achieving a sufficiently large writing current despite the small cell size, 2) a compact read/write separated hierarchy bit/source-line structure with a localized bi-directional write driver for efficiently distributing writing current, and 3) a '1'/'0' dual-array equalized reference cell for stable read operation.

AB - A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ns at a supply voltage of 1.8 V. The chip was fabricated with 150-nm CMOS and a 100 × 200 nm tunnel magnetoresistive device element. This chip features three ircuit technologies suitable for a large-scale array: 1) a two-transistor, one-resistor (2T1R) type memory cell for achieving a sufficiently large writing current despite the small cell size, 2) a compact read/write separated hierarchy bit/source-line structure with a localized bi-directional write driver for efficiently distributing writing current, and 3) a '1'/'0' dual-array equalized reference cell for stable read operation.

UR - http://www.scopus.com/inward/record.url?scp=70449393678&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=70449393678&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:70449393678

SN - 9784863480018

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - 84

EP - 85

BT - 2009 Symposium on VLSI Circuits

T2 - 2009 Symposium on VLSI Circuits

Y2 - 16 June 2009 through 18 June 2009

ER -