3.2-Gb/s 1024-b rate-1/2 LDPC decoder chip using a flooding-type update-schedule algorithm

Naoya Onizawa, Tomokazu Ikeda, Takahiro Hanyu, Vincent C. Gaudet

研究成果: Conference contribution

13 被引用数 (Scopus)

抄録

This paper presents a high-speed low-density parity-check (LDPC) decoder chip using a new decoding algorithm, called a flooding-type update-schedule algorithm. Since node computations are performed using partially updated messages in the proposed algorithm, because of the good similarity among time-consecutive messages, data-transmission bottleneck between nodes for node computation is greatly reduced. Moreover, longer wires between nodes are appropriately divided into several subwires by inserting flip-flops so that system clock frequency for the LDPC decoding scheme can be much increased while maintaining the same BER as a conventional algorithm using fully updated messages. In fact, a throughput of 3.2Gb/s in a 1024-b LDPC decoder chip under 90nm CMOS technology is attained with the sufficient BER.

本文言語English
ホスト出版物のタイトル2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference Proceedings
ページ217-220
ページ数4
DOI
出版ステータスPublished - 2007 12 1
イベント2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference - Montreal, QC, Canada
継続期間: 2007 8 52007 8 8

出版物シリーズ

名前Midwest Symposium on Circuits and Systems
ISSN(印刷版)1548-3746

Other

Other2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference
国/地域Canada
CityMontreal, QC
Period07/8/507/8/8

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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