1T1MTJ STT-MRAM Cell Array Design with an Adaptive Reference Voltage Generator for Improving Device Variation Tolerance

Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Tosinari Watanabe, Hideo Sato, Soshi Sato, Takashi Nasuno, Yasuo Noguchi, Mitsuo Yasuhira, Takaho Tanigawa, Masakazu Muraguchi, Masaaki Niwa, Kenchi Ito, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh

研究成果: Conference contribution

12 被引用数 (Scopus)

抄録

A device-variation-tolerant spin-transfer-torque magnetic random access memory (STT-MRAM) cell array design with a high-signal-margin reference generator circuit was developed to create high-density 1T1MTJ STT-MRAMs. To realize an appropriate STT-MRAM design, fluctuations in the memory cell characteristics were first measured using a 1-kbit STT-MRAM test chip. Based on these measurements, a reference generator and an STT-MRAM cell array architecture were proposed. This cell array was evaluated in terms of the signal margin for read operation and its tolerance to device variation by means of Monte-Carlo SPICE circuit simulations. The proposed design enables a 50% improvement in the signal margin compared with the conventional cell array circuit.

本文言語English
ホスト出版物のタイトル2015 IEEE 7th International Memory Workshop, IMW 2015
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9781467369312
DOI
出版ステータスPublished - 2015 7 2
イベント2015 7th IEEE International Memory Workshop, IMW 2015 - Monterey, United States
継続期間: 2015 5 172015 5 20

出版物シリーズ

名前2015 IEEE 7th International Memory Workshop, IMW 2015

Other

Other2015 7th IEEE International Memory Workshop, IMW 2015
国/地域United States
CityMonterey
Period15/5/1715/5/20

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • ソフトウェア
  • 電子工学および電気工学
  • コンピュータ サイエンスの応用

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