1T-1MTJ Type Embedded STT-MRAM with Advanced Low-Damage and Short-Failure-Free RIE Technology down to 32 nmφ MTJ Patterning

Hideo Sato, Toshinari Watanabe, Hiroki Koike, Takashi Saito, Sadahiko Miura, Hiroaki Honjo, Hirofumi Inoue, Shoji Ikeda, Yasuo Noguchi, Takaho Tanigawa, Mitsuo Yasuhira, Hideo Ohno, Song Yun Kang, Takuya Kubo, Koichi Takatsuki, Koji Yamashita, Yasushi Yagi, Ryo Tamura, Takuro Nishimura, Koh MurataTetsuo Endoh

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

We have successfully developed advanced low-damage and short-failure-free RIE technology under 300 mm process down to 32 nmφ MTJ patterning. By using the developed RIE technology, we have achieved significant improvement in TMR ratio, coercivity, thermal stability factor, and the ratio of thermal stability factor to intrinsic critical current compared to those using conventional RIE technology. By using our advanced RIE technology, we also fabricated 1T-1MTJ type embedded 2Mb-STT-MRAM chips with the 61 nmφ-perpendicular-MTJs using the double-MgO free layer under 90 nm CMOS-MTJ hybrid 300 mm process. Advantage of our advanced RIE technology has been demonstrated with their high yield and excellent shmoo plot. The STT-MRAM technology with high-performance MTJ using low-damage RIE patterning process contributes to future high-density embedded STT-MRAM.

本文言語English
ホスト出版物のタイトル2018 IEEE 10th International Memory Workshop, IMW 2018
出版社Institute of Electrical and Electronics Engineers Inc.
ページ1-4
ページ数4
ISBN(電子版)9781538652473
DOI
出版ステータスPublished - 2018 6 19
イベント10th IEEE International Memory Workshop, IMW 2018 - Kyoto, Japan
継続期間: 2018 5 132018 5 16

出版物シリーズ

名前2018 IEEE 10th International Memory Workshop, IMW 2018

Other

Other10th IEEE International Memory Workshop, IMW 2018
国/地域Japan
CityKyoto
Period18/5/1318/5/16

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子材料、光学材料、および磁性材料

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