14ns write speed 128Mb density Embedded STT-MRAM with endurance>10                         10                          and 10yrs retention@85°C using novel low damage MTJ integration process

H. Sato; H. Honjo; T. Watanabe; M. Niwa; H. Koike; S. Miura; T. Saito; H. Inoue; T. Nasuno; T. Tanigawa; Y. Noguchi; T. Yoshiduka; M. Yasuhira; S. Ikeda; S. Y. Kang; T. Kubo; K. Yamashita; Y. Yagi; R. Tamura; T. Endoh

doi:10.1109/IEDM.2018.8614606

14ns write speed 128Mb density Embedded STT-MRAM with endurance>10 ¹⁰ and 10yrs retention@85°C using novel low damage MTJ integration process

H. Sato, H. Honjo, T. Watanabe, M. Niwa, H. Koike, S. Miura, T. Saito, H. Inoue, T. Nasuno, T. Tanigawa, Y. Noguchi, T. Yoshiduka, M. Yasuhira, S. Ikeda, S. Y. Kang, T. Kubo, K. Yamashita, Y. Yagi, R. Tamura, T. Endoh

研究成果: Conference contribution

12 被引用数 (Scopus)

抄録

Novel damage control integration process technology has been developed through development of new low-damage MgO deposition process, low-damage RIE process, and low temperature SiN-cap process. Application of the developed damage control integration process technology to MTJ fabrication enabled us to demonstrate an improvement of TMR ratio, thermal stability factor, and switching efficiency. Moreover, it is shown that the endurance of the fabricated MTJs is over 10 ¹⁰ , although thermal stability factor drastically increased. Finally, with the developed 37-nm p-MTJ technology and the damage control integration process technology, 128Mb density embedded STT-MRAM was fabricated. By using our 128Mb density STT-MRAM, 14ns write speed at V dd of 1.2V was successfully demonstrated. This result will contribute to low power MCU/IoT chip solution and so on.

本文言語	English
ホスト出版物のタイトル	2018 IEEE International Electron Devices Meeting, IEDM 2018
出版社	Institute of Electrical and Electronics Engineers Inc.
ページ	27.2.1-27.2.4
ISBN（電子版）	9781728119878
DOI	https://doi.org/10.1109/IEDM.2018.8614606
出版ステータス	Published - 2019 1 16
イベント	64th Annual IEEE International Electron Devices Meeting, IEDM 2018 - San Francisco, United States 継続期間: 2018 12 1 → 2018 12 5

出版物シリーズ

名前	Technical Digest - International Electron Devices Meeting, IEDM
巻	2018-December
ISSN（印刷版）	0163-1918

Conference

Conference	64th Annual IEEE International Electron Devices Meeting, IEDM 2018
国/地域	United States
City	San Francisco
Period	18/12/1 → 18/12/5

ASJC Scopus subject areas

電子材料、光学材料、および磁性材料
凝縮系物理学
電子工学および電気工学
材料化学

文献へのアクセス

10.1109/IEDM.2018.8614606

他のファイルとリンク

フィンガープリント

「14ns write speed 128Mb density Embedded STT-MRAM with endurance>10 <sup>10</sup> and 10yrs retention@85°C using novel low damage MTJ integration process」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル

Sato, H., Honjo, H., Watanabe, T., Niwa, M., Koike, H., Miura, S., Saito, T., Inoue, H., Nasuno, T., Tanigawa, T., Noguchi, Y., Yoshiduka, T., Yasuhira, M., Ikeda, S., Kang, S. Y., Kubo, T., Yamashita, K., Yagi, Y., Tamura, R., & Endoh, T. (2019). 14ns write speed 128Mb density Embedded STT-MRAM with endurance>10 ¹⁰ and 10yrs retention@85°C using novel low damage MTJ integration process In 2018 IEEE International Electron Devices Meeting, IEDM 2018 (pp. 27.2.1-27.2.4). [8614606] (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2018-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2018.8614606

14ns write speed 128Mb density Embedded STT-MRAM with endurance>10 ¹⁰ and 10yrs retention@85°C using novel low damage MTJ integration process . / Sato, H.; Honjo, H.; Watanabe, T.; Niwa, M.; Koike, H.; Miura, S.; Saito, T.; Inoue, H.; Nasuno, T.; Tanigawa, T.; Noguchi, Y.; Yoshiduka, T.; Yasuhira, M.; Ikeda, S.; Kang, S. Y.; Kubo, T.; Yamashita, K.; Yagi, Y.; Tamura, R.; Endoh, T.

2018 IEEE International Electron Devices Meeting, IEDM 2018. Institute of Electrical and Electronics Engineers Inc., 2019. p. 27.2.1-27.2.4 8614606 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2018-December).

研究成果: Conference contribution

Sato, H, Honjo, H, Watanabe, T, Niwa, M, Koike, H , Miura, S, Saito, T, Inoue, H, Nasuno, T, Tanigawa, T, Noguchi, Y, Yoshiduka, T, Yasuhira, M, Ikeda, S, Kang, SY, Kubo, T, Yamashita, K, Yagi, Y, Tamura, R & Endoh, T 2019, 14ns write speed 128Mb density Embedded STT-MRAM with endurance>10 ¹⁰ and 10yrs retention@85°C using novel low damage MTJ integration process in 2018 IEEE International Electron Devices Meeting, IEDM 2018., 8614606, Technical Digest - International Electron Devices Meeting, IEDM, vol. 2018-December, Institute of Electrical and Electronics Engineers Inc., pp. 27.2.1-27.2.4, 64th Annual IEEE International Electron Devices Meeting, IEDM 2018, San Francisco, United States, 18/12/1. https://doi.org/10.1109/IEDM.2018.8614606

Sato H, Honjo H, Watanabe T, Niwa M, Koike H , Miura S et al. 14ns write speed 128Mb density Embedded STT-MRAM with endurance>10 ¹⁰ and 10yrs retention@85°C using novel low damage MTJ integration process In 2018 IEEE International Electron Devices Meeting, IEDM 2018. Institute of Electrical and Electronics Engineers Inc. 2019. p. 27.2.1-27.2.4. 8614606. (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2018.8614606

Sato, H. ; Honjo, H. ; Watanabe, T. ; Niwa, M. ; Koike, H. ; Miura, S. ; Saito, T. ; Inoue, H. ; Nasuno, T. ; Tanigawa, T. ; Noguchi, Y. ; Yoshiduka, T. ; Yasuhira, M. ; Ikeda, S. ; Kang, S. Y. ; Kubo, T. ; Yamashita, K. ; Yagi, Y. ; Tamura, R. ; Endoh, T. / 14ns write speed 128Mb density Embedded STT-MRAM with endurance>10 ¹⁰ and 10yrs retention@85°C using novel low damage MTJ integration process 2018 IEEE International Electron Devices Meeting, IEDM 2018. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 27.2.1-27.2.4 (Technical Digest - International Electron Devices Meeting, IEDM).

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abstract = " Novel damage control integration process technology has been developed through development of new low-damage MgO deposition process, low-damage RIE process, and low temperature SiN-cap process. Application of the developed damage control integration process technology to MTJ fabrication enabled us to demonstrate an improvement of TMR ratio, thermal stability factor, and switching efficiency. Moreover, it is shown that the endurance of the fabricated MTJs is over 10 10 , although thermal stability factor drastically increased. Finally, with the developed 37-nm p-MTJ technology and the damage control integration process technology, 128Mb density embedded STT-MRAM was fabricated. By using our 128Mb density STT-MRAM, 14ns write speed at V dd of 1.2V was successfully demonstrated. This result will contribute to low power MCU/IoT chip solution and so on. ",

author = "H. Sato and H. Honjo and T. Watanabe and M. Niwa and H. Koike and S. Miura and T. Saito and H. Inoue and T. Nasuno and T. Tanigawa and Y. Noguchi and T. Yoshiduka and M. Yasuhira and S. Ikeda and Kang, {S. Y.} and T. Kubo and K. Yamashita and Y. Yagi and R. Tamura and T. Endoh",

note = "Funding Information: ACKNOWLEDGMENT This work was supported by STT-MRAM R&D program under Industry-Academic collaboration of CIES consortium, JST-ACCEL, and JST-OPERA. Publisher Copyright: {\textcopyright} 2018 IEEE.; 64th Annual IEEE International Electron Devices Meeting, IEDM 2018 ; Conference date: 01-12-2018 Through 05-12-2018",

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AU - Niwa, M.

AU - Koike, H.

AU - Miura, S.

AU - Saito, T.

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AU - Nasuno, T.

AU - Tanigawa, T.

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AU - Yoshiduka, T.

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AU - Ikeda, S.

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AU - Kubo, T.

AU - Yamashita, K.

AU - Yagi, Y.

AU - Tamura, R.

AU - Endoh, T.

N1 - Funding Information: ACKNOWLEDGMENT This work was supported by STT-MRAM R&D program under Industry-Academic collaboration of CIES consortium, JST-ACCEL, and JST-OPERA. Publisher Copyright: © 2018 IEEE.

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