TY - GEN
T1 - 14ns write speed 128Mb density Embedded STT-MRAM with endurance>10 10 and 10yrs retention@85°C using novel low damage MTJ integration process
AU - Sato, Hideo
AU - Honjo, H.
AU - Watanabe, T.
AU - Niwa, Masaaki
AU - Koike, H.
AU - Miura, S.
AU - Saito, T.
AU - Inoue, H.
AU - Nasuno, T.
AU - Tanigawa, T.
AU - Noguchi, Y.
AU - Yoshiduka, T.
AU - Yasuhira, M.
AU - Ikeda, S.
AU - Kang, S. Y.
AU - Kubo, T.
AU - Yamashita, K.
AU - Yagi, Y.
AU - Tamura, R.
AU - Endoh, T.
N1 - Funding Information:
ACKNOWLEDGMENT This work was supported by STT-MRAM R&D program under Industry-Academic collaboration of CIES consortium, JST-ACCEL, and JST-OPERA.
Publisher Copyright:
© 2018 IEEE.
PY - 2019/1/16
Y1 - 2019/1/16
N2 - Novel damage control integration process technology has been developed through development of new low-damage MgO deposition process, low-damage RIE process, and low temperature SiN-cap process. Application of the developed damage control integration process technology to MTJ fabrication enabled us to demonstrate an improvement of TMR ratio, thermal stability factor, and switching efficiency. Moreover, it is shown that the endurance of the fabricated MTJs is over 10 10 , although thermal stability factor drastically increased. Finally, with the developed 37-nm p-MTJ technology and the damage control integration process technology, 128Mb density embedded STT-MRAM was fabricated. By using our 128Mb density STT-MRAM, 14ns write speed at V dd of 1.2V was successfully demonstrated. This result will contribute to low power MCU/IoT chip solution and so on.
AB - Novel damage control integration process technology has been developed through development of new low-damage MgO deposition process, low-damage RIE process, and low temperature SiN-cap process. Application of the developed damage control integration process technology to MTJ fabrication enabled us to demonstrate an improvement of TMR ratio, thermal stability factor, and switching efficiency. Moreover, it is shown that the endurance of the fabricated MTJs is over 10 10 , although thermal stability factor drastically increased. Finally, with the developed 37-nm p-MTJ technology and the damage control integration process technology, 128Mb density embedded STT-MRAM was fabricated. By using our 128Mb density STT-MRAM, 14ns write speed at V dd of 1.2V was successfully demonstrated. This result will contribute to low power MCU/IoT chip solution and so on.
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U2 - 10.1109/IEDM.2018.8614606
DO - 10.1109/IEDM.2018.8614606
M3 - Conference contribution
AN - SCOPUS:85061808243
T3 - Technical Digest - International Electron Devices Meeting, IEDM
SP - 27.2.1-27.2.4
BT - 2018 IEEE International Electron Devices Meeting, IEDM 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 64th Annual IEEE International Electron Devices Meeting, IEDM 2018
Y2 - 1 December 2018 through 5 December 2018
ER -