Indoor communication is desired in CMOS millimeter-wave transceivers. To realize indoor communication, a power amplifier with a high RF output power without compromising gain, bandwidth or power efficiency is required. In this paper, a strategic design for gate width selection and matching-network optimization is introduced. A power amplifier is fabricated using a 40nm CMOS technology process with a chip area of 0.30mm2 and a power consumption of 89.1mW at 1.1V DC supply. Its peak gain is 16.8dB at 133GHz and its 3dB bandwidth is 13.0GHz. Its output-referred 1dB compression point is 6.8dBm, its saturated output power is 8.6dBm and its peak power added efficiency is 7.4%. The performance of this power amplifier is evaluated using an indicator and it is confirmed that it has the best performance among power amplifiers over 100GHz.