0.8 μm BiCMOS process with high resistivity substrate for L-band Si-MMIC applications

Takashi Nakashima, Shunji Kubo, Yoshitaka Otsu, Tatsuhiko Ikeda, Noriharu Suematsu, Masao Yamawaki, Tadashi Hirao

研究成果: Paper査読

9 被引用数 (Scopus)

抄録

This paper describes a BiCMOS process for L-band Si-MMIC applications. Low loss transmission line, high performance bipolar transistor (emitter minimum size approximately 0.5 μm), 0.81 μm CMOS, and Schottky diode are integrated on a high resistivity silicon substrate (HRS). Losses of two types of transmission lines, which are composed of multilevel metal layers, are investigated in both high and low resistivity substrates. A low noise amplifier (LNA) is fabricated on a conventional low resistivity silicon substrate.

本文言語English
ページ134-137
ページ数4
出版ステータスPublished - 1996 12 1
外部発表はい
イベントProceedings of the 1996 IEEE Bipolar/BiCMOS Circuits and Technology Meeting - Minneapolis, MN, USA
継続期間: 1996 9 291996 10 1

Other

OtherProceedings of the 1996 IEEE Bipolar/BiCMOS Circuits and Technology Meeting
CityMinneapolis, MN, USA
Period96/9/2996/10/1

ASJC Scopus subject areas

  • 電子工学および電気工学

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