Yield enhancement and mitigating the Si-chipping and wafer cracking in ultra-Thin 20μm-Thick 8-and 12-inch LSI wafer

M. Murugesan, T. Fukushima, J. C. Bea, K. W. Lee, M. Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

We have meticulously investigated several pre-grinding parameters such as edge trimming width, depth, and edge-back rinse of smeared glue to mitigate the Si chipping and cracking and to enhance the yield in ultra-Thin LSI wafer thinning for the thickness value of up to 20 μm, with respect to different types of temporary bonding glue and the glue thickness. After optimizing several pre-grinding and the post-grinding parameters, we found that an intermediate edge-back-rinse process before the final grinding tremendously reduces the Si chipping and wafer cracking, which enhances the yield of ultra-Thin wafer grinding.

Original languageEnglish
Title of host publication2015 26th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages435-439
Number of pages5
ISBN (Electronic)9781479999309
DOIs
Publication statusPublished - 2015 Jul 22
Event26th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2015 - Saratoga Springs, United States
Duration: 2015 May 32015 May 6

Publication series

Name2015 26th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2015

Other

Other26th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2015
CountryUnited States
CitySaratoga Springs
Period15/5/315/5/6

Keywords

  • Si chipping
  • Wafer thinning
  • wafer cracking

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Industrial and Manufacturing Engineering
  • Process Chemistry and Technology

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