Write-Operation Frequency Reduction for Nonvoratile Logic LSI with a Short Break-Even Time

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A technique to save the frequency of write operation on the non-volatile memory is proposed for reducing dynamic power dissipation of non-volatile logic LSI which shortens its break-even time for power gating. The proposed technique is realized by combining a selective write method with a coding technique. The selective write method compares input words and stored words, and rejects redundant write operation. Moreover, the use of the data coding technique shortens the Hamming distance between adjacent words in an input data sequence and reduces the frequency of bit reversal in the non-volatile memory, which results in the further reduction in the power dissipation due to write operation. Through the design and evaluation of a non-volatile 8-bit counter, it is observed that the proposed technique shortens the break-even time for power gating by up to 85.2% with a small hardware overhead.

Original languageEnglish
Title of host publicationProceedings - 2015 IEEE 45th International Symposium on Multiple-Valued Logic, ISMVL 2015
PublisherIEEE Computer Society
Pages152-157
Number of pages6
ISBN (Electronic)9781479917778
DOIs
Publication statusPublished - 2015 Sep 2
Event45th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2015 - Waterloo, Canada
Duration: 2015 May 182015 May 20

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
Volume2015-September
ISSN (Print)0195-623X

Other

Other45th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2015
CountryCanada
CityWaterloo
Period15/5/1815/5/20

Keywords

  • data coding
  • nonvolatile memory
  • power gating
  • selective write method
  • write-operation frequency

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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  • Cite this

    Akutsu, T., Natsui, M., & Hanyu, T. (2015). Write-Operation Frequency Reduction for Nonvoratile Logic LSI with a Short Break-Even Time. In Proceedings - 2015 IEEE 45th International Symposium on Multiple-Valued Logic, ISMVL 2015 (pp. 152-157). [7238150] (Proceedings of The International Symposium on Multiple-Valued Logic; Vol. 2015-September). IEEE Computer Society. https://doi.org/10.1109/ISMVL.2015.18