Write-Operation Frequency Reduction for Nonvoratile Logic LSI with a Short Break-Even Time

Takeaki Akutsu; Masanori Natsui; Takahiro Hanyu

doi:10.1109/ISMVL.2015.18

Write-Operation Frequency Reduction for Nonvoratile Logic LSI with a Short Break-Even Time

Takeaki Akutsu, Masanori Natsui, Takahiro Hanyu

Systems & Software Division

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A technique to save the frequency of write operation on the non-volatile memory is proposed for reducing dynamic power dissipation of non-volatile logic LSI which shortens its break-even time for power gating. The proposed technique is realized by combining a selective write method with a coding technique. The selective write method compares input words and stored words, and rejects redundant write operation. Moreover, the use of the data coding technique shortens the Hamming distance between adjacent words in an input data sequence and reduces the frequency of bit reversal in the non-volatile memory, which results in the further reduction in the power dissipation due to write operation. Through the design and evaluation of a non-volatile 8-bit counter, it is observed that the proposed technique shortens the break-even time for power gating by up to 85.2% with a small hardware overhead.

Original language	English
Title of host publication	Proceedings - 2015 IEEE 45th International Symposium on Multiple-Valued Logic, ISMVL 2015
Publisher	IEEE Computer Society
Pages	152-157
Number of pages	6
ISBN (Electronic)	9781479917778
DOIs	https://doi.org/10.1109/ISMVL.2015.18
Publication status	Published - 2015 Sep 2
Event	45th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2015 - Waterloo, Canada Duration: 2015 May 18 → 2015 May 20

Publication series

Name	Proceedings of The International Symposium on Multiple-Valued Logic
Volume	2015-September
ISSN (Print)	0195-623X

Other

Other	45th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2015
Country	Canada
City	Waterloo
Period	15/5/18 → 15/5/20

Keywords

data coding
nonvolatile memory
power gating
selective write method
write-operation frequency

ASJC Scopus subject areas

Computer Science(all)
Mathematics(all)

Access to Document

10.1109/ISMVL.2015.18

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Akutsu, T., Natsui, M., & Hanyu, T. (2015). Write-Operation Frequency Reduction for Nonvoratile Logic LSI with a Short Break-Even Time. In Proceedings - 2015 IEEE 45th International Symposium on Multiple-Valued Logic, ISMVL 2015 (pp. 152-157). [7238150] (Proceedings of The International Symposium on Multiple-Valued Logic; Vol. 2015-September). IEEE Computer Society. https://doi.org/10.1109/ISMVL.2015.18

Write-Operation Frequency Reduction for Nonvoratile Logic LSI with a Short Break-Even Time. / Akutsu, Takeaki; Natsui, Masanori ; Hanyu, Takahiro.

Proceedings - 2015 IEEE 45th International Symposium on Multiple-Valued Logic, ISMVL 2015. IEEE Computer Society, 2015. p. 152-157 7238150 (Proceedings of The International Symposium on Multiple-Valued Logic; Vol. 2015-September).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Akutsu, T, Natsui, M & Hanyu, T 2015, Write-Operation Frequency Reduction for Nonvoratile Logic LSI with a Short Break-Even Time. in Proceedings - 2015 IEEE 45th International Symposium on Multiple-Valued Logic, ISMVL 2015., 7238150, Proceedings of The International Symposium on Multiple-Valued Logic, vol. 2015-September, IEEE Computer Society, pp. 152-157, 45th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2015, Waterloo, Canada, 15/5/18. https://doi.org/10.1109/ISMVL.2015.18

Akutsu T, Natsui M , Hanyu T. Write-Operation Frequency Reduction for Nonvoratile Logic LSI with a Short Break-Even Time. In Proceedings - 2015 IEEE 45th International Symposium on Multiple-Valued Logic, ISMVL 2015. IEEE Computer Society. 2015. p. 152-157. 7238150. (Proceedings of The International Symposium on Multiple-Valued Logic). https://doi.org/10.1109/ISMVL.2015.18

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abstract = "A technique to save the frequency of write operation on the non-volatile memory is proposed for reducing dynamic power dissipation of non-volatile logic LSI which shortens its break-even time for power gating. The proposed technique is realized by combining a selective write method with a coding technique. The selective write method compares input words and stored words, and rejects redundant write operation. Moreover, the use of the data coding technique shortens the Hamming distance between adjacent words in an input data sequence and reduces the frequency of bit reversal in the non-volatile memory, which results in the further reduction in the power dissipation due to write operation. Through the design and evaluation of a non-volatile 8-bit counter, it is observed that the proposed technique shortens the break-even time for power gating by up to 85.2% with a small hardware overhead.",

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