TY - JOUR
T1 - Work-function engineering for 32-nm-node pMOS devices
T2 - High-performance TaCNO-gated films
AU - O'Sullivan, Barry J.
AU - Mitsuhashi, Riichirou
AU - Ito, Satoru
AU - Oikawa, Kota
AU - Kubicek, Stefan
AU - Paraschiv, Vasile
AU - Adelmann, Christoph
AU - Veloso, Anabela
AU - Yu, Hong
AU - Schram, Tom
AU - Biesemans, Serge
AU - Nakabayashi, T.
AU - Ikeda, Atsushi
AU - Niwa, Masaaki
PY - 2008
Y1 - 2008
N2 - We have demonstrated p-type field effect transistors (p-FETs) devices using a TaCNO metal gate for the first time. These p-FETs have threshold voltage values of -0.4 and -0.25 V for HfSiON and HfSiO gate dielectrics, respectively, with equivalent oxide thickness of 1.6-1.7 nm. The TaCNO metal shows a high effective work function (eWF) of 4.89 eV on thick SiO2 interface layer, although the eWF rolls off with reducing EOT. Excellent transistor characteristics are achieved, with Ion of 275 μΑ/μm at Ioff nΑ, for Vdd =1.1 V.
AB - We have demonstrated p-type field effect transistors (p-FETs) devices using a TaCNO metal gate for the first time. These p-FETs have threshold voltage values of -0.4 and -0.25 V for HfSiON and HfSiO gate dielectrics, respectively, with equivalent oxide thickness of 1.6-1.7 nm. The TaCNO metal shows a high effective work function (eWF) of 4.89 eV on thick SiO2 interface layer, although the eWF rolls off with reducing EOT. Excellent transistor characteristics are achieved, with Ion of 275 μΑ/μm at Ioff nΑ, for Vdd =1.1 V.
KW - High-κ
KW - PFET
KW - TaCNO
KW - Work-function engineering
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U2 - 10.1109/LED.2008.2005214
DO - 10.1109/LED.2008.2005214
M3 - Article
AN - SCOPUS:55249122290
SN - 0741-3106
VL - 29
SP - 1203
EP - 1205
JO - IEEE Electron Device Letters
JF - IEEE Electron Device Letters
IS - 11
ER -