Work-function engineering for 32-nm-node pMOS devices: High-performance TaCNO-gated films

Barry J. O'Sullivan, Riichirou Mitsuhashi, Satoru Ito, Kota Oikawa, Stefan Kubicek, Vasile Paraschiv, Christoph Adelmann, Anabela Veloso, Hong Yu, Tom Schram, Serge Biesemans, T. Nakabayashi, Atsushi Ikeda, Masaaki Niwa

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)


We have demonstrated p-type field effect transistors (p-FETs) devices using a TaCNO metal gate for the first time. These p-FETs have threshold voltage values of -0.4 and -0.25 V for HfSiON and HfSiO gate dielectrics, respectively, with equivalent oxide thickness of 1.6-1.7 nm. The TaCNO metal shows a high effective work function (eWF) of 4.89 eV on thick SiO2 interface layer, although the eWF rolls off with reducing EOT. Excellent transistor characteristics are achieved, with Ion of 275 μΑ/μm at Ioff nΑ, for Vdd =1.1 V.

Original languageEnglish
Pages (from-to)1203-1205
Number of pages3
JournalIEEE Electron Device Letters
Issue number11
Publication statusPublished - 2008
Externally publishedYes


  • High-κ
  • PFET
  • TaCNO
  • Work-function engineering

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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