What can we do about barrier layer scaling to 5 nm node technology ?

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Interconnect-related problems in the advanced technology node are identified and possible solutions are proposed. A PVD process of a double-layer Ta/TaN barrier is to be replaced with a CVD process of a single-layer barrier. Cu filling process can be changed from PVD seed deposition and electroplating to dynamic PVD reflow of Cu. Manganese and its oxide are shown as a possible choice of new barrier materials.

Original languageEnglish
Title of host publicationDigest of Technical Papers - Symposium on VLSI Technology
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479933310
DOIs
Publication statusPublished - 2014 Sep 8
Event34th Symposium on VLSI Technology, VLSIT 2014 - Honolulu, United States
Duration: 2014 Jun 92014 Jun 12

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Other

Other34th Symposium on VLSI Technology, VLSIT 2014
CountryUnited States
CityHonolulu
Period14/6/914/6/12

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Koike, J. (2014). What can we do about barrier layer scaling to 5 nm node technology ? In Digest of Technical Papers - Symposium on VLSI Technology [6894408] (Digest of Technical Papers - Symposium on VLSI Technology). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2014.6894408