Wafer-scale fabrication of transistors using CVD-grown graphene and its application to inverter circuit

Shu Nakaharai, Tomohiko Iijima, Shinichi Ogawa, Katsunori Yagi, Naoki Harada, Kenjiro Hayashi, Daiyu Kondo, Makoto Takahashi, Songlin Li, Kazuhito Tsukagoshi, Shintaro Sato, Naoki Yokoyama

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)

Abstract

Graphene transistors were fabricated by a wafer-scale "top-down" process using a graphene sheet formed by the chemical vapor deposition (CVD) method. The devices have a dual-gated structure with an ion-irradiated channel, in which transistor polarity can be electrostatically controlled. We demonstrated, at room temperature, an on/off operation of current and electrostatic control of transistor polarity. By combining two dual-gated transistors, a six-terminal device was fabricated with three top gates and two ion-irradiated channels. In this device, we demonstrated an inverter operation.

Original languageEnglish
Article number04DN06
JournalJapanese journal of applied physics
Volume54
Issue number4
DOIs
Publication statusPublished - 2015 Apr 1
Externally publishedYes

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)

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