Wafer level packaging of MEMS

Masayoshi Esashi

Research output: Contribution to journalArticlepeer-review

298 Citations (Scopus)

Abstract

Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass-Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in many cases. On the other hand, lateral electrical interconnections on the surface of the chip are used for bonding with intermediate melting materials, such as low melting point glass and solder. The cavity formed by surface micromachining is made using sacrificial etching, and the openings needed for the sacrificial etching are plugged using deposition sealing methods. Vacuum packaging methods and the structures for electrical feedthrough for the interconnection are discussed in this review.

Original languageEnglish
Article number073001
JournalJournal of Micromechanics and Microengineering
Volume18
Issue number7
DOIs
Publication statusPublished - 2008 Aug 1

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Mechanics of Materials
  • Mechanical Engineering
  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'Wafer level packaging of MEMS'. Together they form a unique fingerprint.

Cite this