This paper describes the new wafer level packaging process with the diced chip array on the small-diameter handling wafer. The general purpose of wafer level packaging is to realize a smaller, more functional and cost effective electronic package. For example, Wafer Level chip size package and Wafer stacking 3D package are the most effective packaging processes/structures using semiconductor wafer process. In the semiconductor industrial trend, silicon wafer sizes become larger to achieve a higher chip throughput and to reduce a chip cost. However in actual applications, the packaging needs are diversified and the required number of each package type does not meet the huge sized wafer processing. In this paper, we introduce the new packaging technique. In this new technique, after dicing CMOS wafer to the individual chips, we rearrange them on another smaller handling wafer. We, then, planarize the surface after filling up the resin on it, which can be used just like a single wafer. As the result, we can have a free hand to choose the size of handling wafer, and it means that we can use the existing equipment, which leads to lower cost and shorter development time. First, the influence of residual stress after rearranging the matrix of chip on the handling wafer was investigated with using FEM-modeling. It was found that the both of the sell size of the matrix and the material properties of the filled resin greatly influence on the wafer warpage, and that the design of matrix and the material of resin are key to complete the process of this new technique. Second, we tried to apply this new technique to an image sensor. 8×8 matrix of 9mm2 CMOS image sensor chips are rearranged on 4inch glass wafer, and we fabricated TSVs in the image sensor chips for chip size package.