Vth-variation compensation of multiple-valued current-mode circuit using TMR devices

Akihiro Hirosaki; Masatomo Miura; Atsushi Matsumoto; Takahiro Hanyu

doi:10.1109/ISMVL.2008.13

V_th-variation compensation of multiple-valued current-mode circuit using TMR devices

Akihiro Hirosaki, Masatomo Miura, Atsushi Matsumoto, Takahiro Hanyu

Systems & Software Division

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A compensation method against a threshold-voltage (V_th) variation using tunneling magnetoresistive (TMR) devices, is proposed for a deep-submicron VLSI. The influence of the V_th variation in a single MOS transistor can be neglected by adjusting the source voltage of the MOS transistor. The desired circuit behavior is obtained by programming the resistance value of a TMR device which is connected to the MOS transistor in series. By using HSPICE simulation under a 90nm CMOS technology, it is demonstrated that a radix-2 signed-digit adder using the proposed method is robust against the V_th variation.

Original language	English
Title of host publication	Proceedings - 38th International Symposium on Multiple-Valued Logic, ISMVL 2008
Pages	14-19
Number of pages	6
DOIs	https://doi.org/10.1109/ISMVL.2008.13
Publication status	Published - 2008 Sep 3
Event	38th International Symposium on Multiple-Valued Logic, ISMVL 2008 - Dallas, TX, United States Duration: 2008 May 22 → 2008 May 24

Publication series

Name	Proceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)	0195-623X

Other

Other	38th International Symposium on Multiple-Valued Logic, ISMVL 2008
Country/Territory	United States
City	Dallas, TX
Period	08/5/22 → 08/5/24

ASJC Scopus subject areas

Computer Science(all)
Mathematics(all)

Access to Document

10.1109/ISMVL.2008.13

Cite this

V_th-variation compensation of multiple-valued current-mode circuit using TMR devices. / Hirosaki, Akihiro; Miura, Masatomo; Matsumoto, Atsushi; Hanyu, Takahiro.

Proceedings - 38th International Symposium on Multiple-Valued Logic, ISMVL 2008. 2008. p. 14-19 4539395 (Proceedings of The International Symposium on Multiple-Valued Logic).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hirosaki, A, Miura, M, Matsumoto, A & Hanyu, T 2008, V_th-variation compensation of multiple-valued current-mode circuit using TMR devices. in Proceedings - 38th International Symposium on Multiple-Valued Logic, ISMVL 2008., 4539395, Proceedings of The International Symposium on Multiple-Valued Logic, pp. 14-19, 38th International Symposium on Multiple-Valued Logic, ISMVL 2008, Dallas, TX, United States, 08/5/22. https://doi.org/10.1109/ISMVL.2008.13

@inproceedings{c0c68912c2f4466586fb242b7f65d86a,

title = "Vth-variation compensation of multiple-valued current-mode circuit using TMR devices",

abstract = "A compensation method against a threshold-voltage (Vth) variation using tunneling magnetoresistive (TMR) devices, is proposed for a deep-submicron VLSI. The influence of the Vth variation in a single MOS transistor can be neglected by adjusting the source voltage of the MOS transistor. The desired circuit behavior is obtained by programming the resistance value of a TMR device which is connected to the MOS transistor in series. By using HSPICE simulation under a 90nm CMOS technology, it is demonstrated that a radix-2 signed-digit adder using the proposed method is robust against the Vth variation.",

author = "Akihiro Hirosaki and Masatomo Miura and Atsushi Matsumoto and Takahiro Hanyu",

year = "2008",

month = sep,

day = "3",

doi = "10.1109/ISMVL.2008.13",

language = "English",

isbn = "9780769531557",

series = "Proceedings of The International Symposium on Multiple-Valued Logic",

pages = "14--19",

booktitle = "Proceedings - 38th International Symposium on Multiple-Valued Logic, ISMVL 2008",

note = "38th International Symposium on Multiple-Valued Logic, ISMVL 2008 ; Conference date: 22-05-2008 Through 24-05-2008",

}

TY - GEN

T1 - Vth-variation compensation of multiple-valued current-mode circuit using TMR devices

AU - Hirosaki, Akihiro

AU - Miura, Masatomo

AU - Matsumoto, Atsushi

AU - Hanyu, Takahiro

PY - 2008/9/3

Y1 - 2008/9/3

N2 - A compensation method against a threshold-voltage (Vth) variation using tunneling magnetoresistive (TMR) devices, is proposed for a deep-submicron VLSI. The influence of the Vth variation in a single MOS transistor can be neglected by adjusting the source voltage of the MOS transistor. The desired circuit behavior is obtained by programming the resistance value of a TMR device which is connected to the MOS transistor in series. By using HSPICE simulation under a 90nm CMOS technology, it is demonstrated that a radix-2 signed-digit adder using the proposed method is robust against the Vth variation.

AB - A compensation method against a threshold-voltage (Vth) variation using tunneling magnetoresistive (TMR) devices, is proposed for a deep-submicron VLSI. The influence of the Vth variation in a single MOS transistor can be neglected by adjusting the source voltage of the MOS transistor. The desired circuit behavior is obtained by programming the resistance value of a TMR device which is connected to the MOS transistor in series. By using HSPICE simulation under a 90nm CMOS technology, it is demonstrated that a radix-2 signed-digit adder using the proposed method is robust against the Vth variation.

UR - http://www.scopus.com/inward/record.url?scp=50449092382&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=50449092382&partnerID=8YFLogxK

U2 - 10.1109/ISMVL.2008.13

DO - 10.1109/ISMVL.2008.13

M3 - Conference contribution

AN - SCOPUS:50449092382

SN - 9780769531557

T3 - Proceedings of The International Symposium on Multiple-Valued Logic

SP - 14

EP - 19

BT - Proceedings - 38th International Symposium on Multiple-Valued Logic, ISMVL 2008

T2 - 38th International Symposium on Multiple-Valued Logic, ISMVL 2008

Y2 - 22 May 2008 through 24 May 2008

ER -