TY - GEN
T1 - Vth-variation compensation of multiple-valued current-mode circuit using TMR devices
AU - Hirosaki, Akihiro
AU - Miura, Masatomo
AU - Matsumoto, Atsushi
AU - Hanyu, Takahiro
PY - 2008/9/3
Y1 - 2008/9/3
N2 - A compensation method against a threshold-voltage (Vth) variation using tunneling magnetoresistive (TMR) devices, is proposed for a deep-submicron VLSI. The influence of the Vth variation in a single MOS transistor can be neglected by adjusting the source voltage of the MOS transistor. The desired circuit behavior is obtained by programming the resistance value of a TMR device which is connected to the MOS transistor in series. By using HSPICE simulation under a 90nm CMOS technology, it is demonstrated that a radix-2 signed-digit adder using the proposed method is robust against the Vth variation.
AB - A compensation method against a threshold-voltage (Vth) variation using tunneling magnetoresistive (TMR) devices, is proposed for a deep-submicron VLSI. The influence of the Vth variation in a single MOS transistor can be neglected by adjusting the source voltage of the MOS transistor. The desired circuit behavior is obtained by programming the resistance value of a TMR device which is connected to the MOS transistor in series. By using HSPICE simulation under a 90nm CMOS technology, it is demonstrated that a radix-2 signed-digit adder using the proposed method is robust against the Vth variation.
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U2 - 10.1109/ISMVL.2008.13
DO - 10.1109/ISMVL.2008.13
M3 - Conference contribution
AN - SCOPUS:50449092382
SN - 9780769531557
T3 - Proceedings of The International Symposium on Multiple-Valued Logic
SP - 14
EP - 19
BT - Proceedings - 38th International Symposium on Multiple-Valued Logic, ISMVL 2008
T2 - 38th International Symposium on Multiple-Valued Logic, ISMVL 2008
Y2 - 22 May 2008 through 24 May 2008
ER -