VLSI processor for reliable stereo matching based on window-parallel logic-in-memory architecture

Masanori Hariyama, Michitaka Kameyama

Research output: Contribution to conferencePaperpeer-review

13 Citations (Scopus)

Abstract

This paper presents a VLSI processor for reliable stereo matching to establish correspondence between images by selecting a desirable window size for sum of absolute differences (SAD) computation. In SAD computation, a degree of parallelism between pixels in a window changes depending on its window size, while a degree of parallelism between windows is predetermined by the input-image size. Based on this consideration, a window-parallel and pixel-serial architecture is also proposed to achieve 100% utilization of processing elements. Not only 100% utilization but also a simple interconnection network between memory modules and processing elements makes the VLSI processor much superior to the pixel-parallel-architecture-based VLSI processors.

Original languageEnglish
Pages166-169
Number of pages4
Publication statusPublished - 2004 Sep 29
Event2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI - Honolulu, HI, United States
Duration: 2004 Jun 172004 Jun 19

Other

Other2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI
CountryUnited States
CityHonolulu, HI
Period04/6/1704/6/19

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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