Abstract
VLSI-oriented arithmetic circuits based on the signed-digital (SD) number system are proposed. A new bidirectional current-mode circuit in MOS technology is effectively used for SD number arithmetic operations. The circuit interconnections can be drastically reduced in spite of the redundant SD number representation. A VLSI-oriented, very fast SD multiplier is designed that is based on parallel binary-tree addition scheme. The multiply time of an SD array multiplier based on 2- mu m design rules is less than 30 ns.
Original language | English |
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Title of host publication | Proceedings of The International Symposium on Multiple-Valued Logic |
Publisher | IEEE |
Pages | 70-77 |
Number of pages | 8 |
ISBN (Print) | 0818606991 |
Publication status | Published - 1986 Jan 1 |
ASJC Scopus subject areas
- Chemical Health and Safety
- Hardware and Architecture
- Safety, Risk, Reliability and Quality
- Logic