VLSI architecture for quadtree-based fractal image coding

A VLSI architecture for flexible-size fractal image coding is proposed. The main features of this architecture are that it is capable of performing fractal image coding based on quadtree partitioning without the external memory for the fixed domain pool and uses only local data communication. Since large domain blocks consist of small domain blocks, the calculations of distortion for all kinds of domain block are performed using only the domain pool, which is extracted from the smallest range blocks of the neighbouring processors. This architecture has a fast comparison module which can compute the distortions between a range block and the eight isometric transformations of domain blocks by one full rotation around the centre.